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git01.mediatek.com / filogic / uboot / f4bdf1b148414eb0e356a39d2d8c92a9d6de0017 / arch / riscv / cpu / start.S
  1. b9ad45d riscv: update fix_rela_dyn by Marcus Comstedt · Sun Aug 11 14:45:29 2019 +0200
  2. 2a2a925 riscv: support SPL stack and global data relocation by Lukas Auer · Wed Aug 21 21:14:46 2019 +0200
  3. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  4. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  5. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  6. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · Tue Apr 30 13:49:35 2019 +0800
  7. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  8. cddde09 riscv: hang if relocation of secondary harts fails by Lukas Auer · Sun Mar 17 19:28:40 2019 +0100
  9. 9ebf294 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · Sun Mar 17 19:28:39 2019 +0100
  10. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  11. 8de4b3e riscv: save hart ID in register tp instead of s0 by Lukas Auer · Sun Mar 17 19:28:36 2019 +0100
  12. 01558e2 riscv: delay initialization of caches and debug UART by Lukas Auer · Sun Mar 17 19:28:35 2019 +0100
  13. 89681a7 riscv: Save boot hart id to the global data by Bin Meng · Wed Dec 12 06:12:45 2018 -0800
  14. 2e128a7 riscv: Move trap handler codes to mtrap.S by Bin Meng · Wed Dec 12 06:12:41 2018 -0800
  15. 2a21815 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · Mon Dec 03 17:48:20 2018 +0800
  16. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  17. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  18. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · Thu Nov 22 11:26:29 2018 +0100
  19. 8598e6b riscv: do not blindly modify the mstatus CSR by Lukas Auer · Thu Nov 22 11:26:28 2018 +0100
  20. 230ab8a riscv: remove unused labels in start.S by Lukas Auer · Thu Nov 22 11:26:27 2018 +0100
  21. ccd035a Drop CONFIG_INIT_CRITICAL by Bin Meng · Thu Nov 22 11:26:26 2018 +0100
  22. af51285 riscv: align mtvec on a 4-byte boundary by Lukas Auer · Thu Nov 22 11:26:25 2018 +0100
  23. 7cf4368 riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · Thu Nov 22 11:26:24 2018 +0100
  24. bcb3843 riscv: Make start.S available for all targets by Bin Meng · Wed Sep 26 06:55:17 2018 -0700[Renamed from arch/riscv/cpu/ax25/start.S]
  25. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800[Renamed from arch/riscv/cpu/nx25/start.S]
  26. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  27. 40a6fe7 riscv: ae250: Support DT provided by the board at runtime by Rick Chen · Thu Mar 29 10:08:33 2018 +0800
  28. e76b804 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · Tue Dec 26 13:55:48 2017 +0800