Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e464d6ebc703beeedf04ebbd68f77005d9359067 / arch / riscv / Kconfig
  1. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  2. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  3. 4216f34 riscv: Add Microchip MPFS Icicle board support by Padmarao Begari · Tue May 28 15:47:51 2019 +0530
  4. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  5. ba64b8b CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig by Trevor Woerner · Fri May 03 09:40:59 2019 -0400
  6. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  7. 7376677 riscv: Add a SYSCON driver for Andestech's PLMT by Rick Chen · Tue Apr 02 15:56:40 2019 +0800
  8. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800
  9. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  10. e79178b riscv: implement IPI platform functions using SBI by Lukas Auer · Sun Mar 17 19:28:34 2019 +0100
  11. 83d573d riscv: add infrastructure for calling functions on other harts by Lukas Auer · Sun Mar 17 19:28:32 2019 +0100
  12. 7a167f2 riscv: Add SiFive FU540 board support by Anup Patel · Mon Feb 25 08:15:19 2019 +0000
  13. 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · Mon Feb 25 08:14:10 2019 +0000
  14. dada2d1 riscv: Enlarge the default SYS_MALLOC_F_LEN by Bin Meng · Wed Dec 12 06:12:33 2018 -0800
  15. 8fa4478 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · Wed Dec 12 06:12:32 2018 -0800
  16. f3c8479 riscv: Implement riscv_get_time() API using rdtime instruction by Anup Patel · Wed Dec 12 06:12:31 2018 -0800
  17. b6ee5e1 riscv: Add a SYSCON driver for SiFive's Core Local Interruptor by Bin Meng · Wed Dec 12 06:12:30 2018 -0800
  18. 2788177 riscv: Introduce a Kconfig option for machine mode by Anup Patel · Wed Dec 12 06:12:29 2018 -0800
  19. ecc5d83 riscv: add Kconfig entries for the code model by Lukas Auer · Wed Dec 12 06:12:23 2018 -0800
  20. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  21. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  22. 002012f riscv: add Kconfig entries for the C and A ISA extensions by Lukas Auer · Thu Nov 22 11:26:14 2018 +0100
  23. 7ab1df0 riscv: select CONFIG_PHYS_64BIT on RV64I systems by Lukas Auer · Thu Nov 22 11:26:13 2018 +0100
  24. 54ebfe7 riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I by Lukas Auer · Thu Nov 22 11:26:12 2018 +0100
  25. 8a8694d riscv: Add QEMU virt board support by Bin Meng · Wed Sep 26 06:55:21 2018 -0700
  26. 6b69775 riscv: kconfig: Normalize architecture name spelling by Bin Meng · Wed Sep 26 06:55:06 2018 -0700
  27. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800
  28. 64d4ead riscv: Add Kconfig to support RISC-V by Rick Chen · Tue Dec 26 13:55:52 2017 +0800