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filogic
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uboot
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df89b50c808cc20bff363bbbcc456a28d0540453
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arch
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riscv
f1ac8fa
riscv: cpu: fu740: Fix typo of date
by Zong Li
· Mon Aug 02 15:34:14 2021 +0800
5629aaa
efi_loader: add Linux magic to RISC-V crt0
by Heinrich Schuchardt
· Fri May 28 22:24:37 2021 +0200
bccfc2e
i2c: Rename SPL/TPL_I2C_SUPPORT to I2C
by Simon Glass
· Sat Jul 10 21:14:36 2021 -0600
288ad1f
board: sifive: drop stuff related to unmatched revision 1
by Zong Li
· Tue Jul 20 14:26:08 2021 +0800
51744fe
riscv: booti: do not force relocation if force_reloc is not set
by Vitaly Wool
· Tue Apr 06 10:50:16 2021 +0300
babf1cb
riscv: dts: add OpenPiton RISC-V board dts support
by Tianrui Wei
· Wed Jul 07 15:48:22 2021 +0800
bab770a
riscv: dts: add dts for unmatched rev1
by Zong Li
· Wed Jun 30 23:23:49 2021 +0800
dab3e8e
board: sifive: Add an interface to get PCB revision
by Zong Li
· Wed Jun 30 23:23:48 2021 +0800
9627a8e
riscv: sifive: fu740: Support i2c in spl
by Zong Li
· Wed Jun 30 23:23:47 2021 +0800
3376055
riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller
by Zong Li
· Wed Jun 30 23:23:46 2021 +0800
2ef594d
board: riscv: add openpiton-riscv64 SoC support
by Tianrui Wei
· Thu Jul 01 12:54:19 2021 +0800
d3e8b73
Merge tag 'v2021.07-rc5' into next
by Tom Rini
· Mon Jun 28 16:22:13 2021 -0400
e6638b4
k210: dts: Set PLL1 to the same rate as PLL0
by Sean Anderson
· Fri Jun 11 00:16:15 2021 -0400
b6ec26b
riscv: andes_plic: Fix riscv_get_ipi() mask
by Bin Meng
· Tue Jun 15 13:45:57 2021 +0800
2114b47
riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
by Bin Meng
· Fri Jun 04 13:51:13 2021 +0800
85741a2
riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
by Bin Meng
· Fri Jun 04 13:51:12 2021 +0800
cd00421
riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
by Bin Meng
· Fri Jun 04 13:51:11 2021 +0800
996068b
riscv: ae350: dts: Remove the unnecessary space in bootargs
by Bin Meng
· Fri Jun 04 13:51:10 2021 +0800
c907594
riscv: ae350: dts: Add SPDX license header
by Bin Meng
· Fri Jun 04 13:51:09 2021 +0800
26190b8
riscv: cpu: fu740: clear feature disable CSR
by Green Wan
· Thu May 27 06:52:14 2021 -0700
2e5da52
board: sifive: add HiFive Unmatched board support
by Green Wan
· Thu May 27 06:52:13 2021 -0700
e552af3
riscv: dts: add SiFive Unmatched board support
by Green Wan
· Thu May 27 06:52:12 2021 -0700
06a3e40
riscv: dts: add fu740 support
by Green Wan
· Thu May 27 06:52:11 2021 -0700
ecefa5f
drivers: clk: add fu740 support
by Green Wan
· Thu May 27 06:52:08 2021 -0700
7f33743
riscv: cpu: fu740: Add support for cpu fu740
by Green Wan
· Thu May 27 06:52:07 2021 -0700
4bebdd3
treewide: Convert macro and uses of __section(foo) to __section("foo")
by Marek Behún
· Thu May 20 13:23:52 2021 +0200
442d446
riscv: Drop USE_SPL_FIT_GENERATOR
by Bin Meng
· Mon May 10 20:23:41 2021 +0800
6b977a4
riscv: ae350: Switch to use binman to generate u-boot.itb
by Bin Meng
· Mon May 10 20:23:40 2021 +0800
1255ab8
riscv: qemu: Switch to use binman to generate u-boot.itb
by Bin Meng
· Mon May 10 20:23:39 2021 +0800
eada910
riscv: dts: Sort build targets in alphabetical order
by Bin Meng
· Mon May 10 20:23:38 2021 +0800
ced2097
riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
by Bin Meng
· Mon May 10 20:23:35 2021 +0800
ce64bd3
riscv: Group assembly optimized implementation of memory routines into a submenu
by Bin Meng
· Thu May 13 16:46:18 2021 +0800
8a27fcd
riscv: Fix memmove and optimise memcpy when misalign
by Bin Meng
· Thu May 13 16:46:17 2021 +0800
ac95f46
riscv: Fix arch_fixup_fdt always failing without /chosen
by Sean Anderson
· Fri May 14 22:36:16 2021 -0400
614b1d8
riscv: Split SiFive CLINT support between SPL and U-Boot proper
by Bin Meng
· Tue May 11 20:04:12 2021 +0800
b1b3bc0
Revert "riscv: cpu: fu740: clear feature disable CSR"
by Bin Meng
· Mon May 10 17:08:16 2021 +0800
72422b9
riscv: Don't reserve AI ram in k210 dts
by Sean Anderson
· Thu Apr 08 22:13:13 2021 -0400
b23d757
riscv: k210: Use AI as the parent clock of aisram, not PLL1
by Sean Anderson
· Thu Apr 08 22:13:12 2021 -0400
7be6d2b
riscv: k210: Rename airam to aisram
by Sean Anderson
· Thu Apr 08 22:13:11 2021 -0400
e8d9e3a
riscv: Enable some devices pre-relocation
by Sean Anderson
· Thu Apr 08 22:13:09 2021 -0400
968a13f
riscv: cpu: fu740: clear feature disable CSR
by Green Wan
· Sun May 02 23:23:05 2021 -0700
2612080
riscv: cpu: Add callback to init each core
by Green Wan
· Sun May 02 23:23:04 2021 -0700
d62063d
lmb: move CONFIG_LMB in Kconfig
by Patrick Delaunay
· Wed Mar 10 10:16:25 2021 +0100
369d87a
Add support for stack-protector
by Joel Peshkin
· Sun Apr 11 11:21:58 2021 +0200
c88bdaa
riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes
by Bin Meng
· Wed Mar 31 15:24:50 2021 +0800
23caf66
riscv: assembler versions of memcpy, memmove, memset
by Heinrich Schuchardt
· Sat Mar 27 12:37:04 2021 +0100
76eb648
riscv: simplify longjmp
by Heinrich Schuchardt
· Tue Mar 23 19:11:26 2021 +0100
e9ead4a
riscv: sifive: Rename fu540 board to unleashed
by Bin Meng
· Wed Mar 17 11:10:58 2021 +0800
1c30c0e
riscv: Add watchdog bindings for the k210
by Sean Anderson
· Wed Mar 10 21:02:21 2021 -0500
2f00216
cpu: Rename SPL_CPU_SUPPORT to SPL_CPU
by Simon Glass
· Mon Mar 15 18:11:18 2021 +1300
0937c19
riscv: k210: Enable QSPI for spi3
by Sean Anderson
· Thu Feb 04 23:11:19 2021 -0500
b1db71b
Merge branch '2021-02-02-drop-asm_global_data-when-unused'
by Tom Rini
· Mon Feb 15 08:19:40 2021 -0500
440b77f
riscv: Change phys_addr_t and phys_size_t to 64-bit
by Bin Meng
· Sun Jan 31 20:36:04 2021 +0800
489b25a
riscv: Adjust board_get_usable_ram_top() for 32-bit
by Bin Meng
· Sun Jan 31 20:35:57 2021 +0800
3ba929a
common: Drop asm/global_data.h from common header
by Simon Glass
· Fri Oct 30 21:38:53 2020 -0600
5854c3d
riscv: dts: Add device tree for Microchip Icicle Kit
by Padmarao Begari
· Fri Jan 15 08:20:39 2021 +0530
a235d43
riscv: Add DMA 64-bit address support
by Padmarao Begari
· Fri Jan 15 08:20:35 2021 +0530
bb721de
Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next
by Tom Rini
· Tue Jan 05 22:34:43 2021 -0500
e6256ce
Merge tag 'v2021.01-rc5' into next
by Tom Rini
· Tue Jan 05 16:20:26 2021 -0500
65130cd
dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
by Simon Glass
· Mon Dec 28 20:34:56 2020 -0700
2ddd3e0
riscv: Add device tree bindings for SPI
by Sean Anderson
· Fri Oct 16 18:57:54 2020 -0400
fd9571a
spi: dw: Add SoC-specific compatible strings
by Sean Anderson
· Fri Oct 16 18:57:50 2020 -0400
dd5d79b
riscv: Complete efi header for RV32/64
by Leo Yu-Chi Liang
· Mon Nov 16 17:07:41 2020 +0800
b68402d
riscv: Fix efi header size for RV32
by Leo Yu-Chi Liang
· Thu Nov 12 10:09:52 2020 +0800
fa36696
riscv: Fix efi header for RV32
by Atish Patra
· Tue Oct 13 12:23:31 2020 -0700
b881ba8
riscv: reset after crash
by Heinrich Schuchardt
· Wed Dec 02 14:36:26 2020 +0100
4b96c88
riscv: fix the wrong swap value register
by Brad Kim
· Fri Nov 13 20:47:51 2020 +0900
b75b15b
dm: treewide: Rename ..._platdata variables to just ..._plat
by Simon Glass
· Thu Dec 03 16:55:23 2020 -0700
4f1b444
riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller
by Pragnesh Patel
· Sat Nov 14 14:42:35 2020 +0530
2dc5984
riscv: fu540: dts: Correct reg size of clint node
by Pragnesh Patel
· Tue Oct 20 11:03:02 2020 +0530
52a1db7
riscv: Move timer portions of SiFive CLINT to drivers/timer
by Sean Anderson
· Sun Oct 25 21:46:58 2020 -0400
5a23865
timer: Add _TIMER suffix to Andes PLMT Kconfig
by Sean Anderson
· Sun Oct 25 21:46:57 2020 -0400
5abf1f3
riscv: Move Andes PLMT driver to drivers/timer
by Sean Anderson
· Sun Oct 25 21:46:56 2020 -0400
d1b3321
riscv: k210: Reduce DMA block size
by Sean Anderson
· Mon Oct 12 14:18:15 2020 -0400
584a5ee
riscv: Only enable OF_BOARD_FIXUP for S-Mode
by Sean Anderson
· Sat Sep 05 09:22:11 2020 -0400
947fc2d
timer: Return count from timer_ops.get_count
by Sean Anderson
· Wed Oct 07 14:37:44 2020 -0400
36d38fd
riscv: add DT binding for BOOT button on Maix board
by Heinrich Schuchardt
· Mon Sep 14 11:02:05 2020 -0400
6870556
riscv: Add pinmux and gpio bindings for Kendryte K210
by Sean Anderson
· Mon Sep 14 11:02:04 2020 -0400
38ae92e
Merge branch 'next'
by Tom Rini
· Mon Oct 05 13:05:46 2020 -0400
5bdad9f
riscv: Add some comments to start.S
by Sean Anderson
· Mon Sep 21 07:51:41 2020 -0400
2c4c7d1
riscv: Ensure gp is NULL or points to valid data
by Sean Anderson
· Mon Sep 21 07:51:40 2020 -0400
934b24a
riscv: Consolidate fences into AMOs for available_harts_lock
by Sean Anderson
· Mon Sep 21 07:51:39 2020 -0400
dd1cd70
riscv: Clear pending IPIs on initialization
by Sean Anderson
· Mon Sep 21 07:51:38 2020 -0400
ff184fe
riscv: Use a valid bit to ignore already-pending IPIs
by Sean Anderson
· Mon Sep 21 07:51:37 2020 -0400
cfb0809
riscv: Match memory barriers between send_ipi_many and handle_ipi
by Sean Anderson
· Mon Sep 21 07:51:36 2020 -0400
e8de08b
Revert "riscv: Clear pending interrupts before enabling IPIs"
by Sean Anderson
· Mon Sep 21 07:51:35 2020 -0400
3d999194
riscv: Update SiFive device tree for new CLINT driver
by Sean Anderson
· Mon Sep 28 10:52:29 2020 -0400
c6d0ef8
riscv: Update Kendryte device tree for new CLINT driver
by Sean Anderson
· Mon Sep 28 10:52:28 2020 -0400
272ab20
riscv: Rework Sifive CLINT as UCLASS_TIMER driver
by Sean Anderson
· Mon Sep 28 10:52:26 2020 -0400
28bfc32
riscv: Clean up initialization in Andes PLIC
by Sean Anderson
· Mon Sep 28 10:52:25 2020 -0400
87e6ce5
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
by Sean Anderson
· Mon Sep 28 10:52:24 2020 -0400
9baaaef
riscv: Rework riscv timer driver to only support S-mode
by Sean Anderson
· Mon Sep 28 10:52:21 2020 -0400
fbef54d
riscv: restore global data pointer in trap handler
by Heinrich Schuchardt
· Sat Sep 26 07:50:36 2020 +0200
646f8c6
fdtdec: optionally add property no-map to created reserved memory node
by Etienne Carriere
· Thu Sep 10 10:49:59 2020 +0200
6e7eb46
riscv: define function set_gd()
by Heinrich Schuchardt
· Thu Sep 10 07:47:39 2020 +0200
95492ae
cmd: provide command sbi
by Heinrich Schuchardt
· Thu Aug 20 19:43:39 2020 +0200
c78eef7
riscv: fix building with CONFIG_SPL_SMP=n
by Heinrich Schuchardt
· Sat Aug 15 09:49:26 2020 +0200
54bcf26
riscv: fu540: Use correct API to get L2 cache controller base address
by Bin Meng
· Tue Aug 18 01:09:20 2020 -0700
77efe24
riscv: additional crash information
by Heinrich Schuchardt
· Sat Aug 01 15:15:39 2020 +0000
03de50e
riscv: sifive: fu540: redundant initialization
by Heinrich Schuchardt
· Mon Aug 03 23:09:49 2020 +0200
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