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git01.mediatek.com / filogic / uboot / d90e040f3681d51ea7c6fd7cb1aa3c63a15311af / cpu / mpc8xxx
  1. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  2. b834f92 Check DDR interleaving mode by Haiying Wang · 16 years ago
  3. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  4. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  5. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  6. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  7. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  8. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  9. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  10. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago