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git01.mediatek.com / filogic / uboot / d71fec01bc8b20dc5210ba09fab5bcf0cd896d1c / cpu / mpc8xxx / ddr
  1. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  2. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  3. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  4. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  5. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  6. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
  7. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  8. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:32 2008 -0500
  9. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:30 2008 -0500
  10. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500