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git01.mediatek.com / filogic / uboot / d67ad6e3a9550f72dc97c30a12515e7b522799e5 / drivers / clk / renesas / r8a77980-cpg-mssr.c
  1. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  2. 22f9fc7 clk: renesas: Only ever access documented bits in clock driver teardown by Marek Vasut · Sat Apr 25 14:57:45 2020 +0200
  3. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  4. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  5. d52c6cb clk: renesas: Add R8A77980 V3H clock tables by Marek Vasut · Mon Jul 29 19:59:44 2019 +0200