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git01.mediatek.com / filogic / uboot / d0de5dc0fcb2e83d893a424cc1b5ba8a498d7b91 / drivers / clk / renesas / rcar-gen3-cpg.h
  1. ba2c7d2 clk: renesas: Update R-Car Gen3 driver Gen4 support by Marek Vasut · Tue Feb 28 22:34:38 2023 +0100
  2. ea8505e clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching by Marek Vasut · Tue Feb 28 07:25:11 2023 +0100
  3. 6811b57 clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI by Hai Pham · Thu Jan 26 21:06:06 2023 +0100
  4. 4dae076 clk: renesas: Switch to new SD clock handling by Hai Pham · Sun Jan 29 02:50:22 2023 +0100
  5. e83700a clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function by Hai Pham · Thu Jan 26 21:06:03 2023 +0100
  6. a80b061 clk: renesas: Use pre-defined offset for RPC clocks by Hai Pham · Thu Jan 26 21:02:04 2023 +0100
  7. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  8. 569acef clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:56 2023 +0100
  9. d1ff7e0 clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:55 2023 +0100
  10. 0985e0e clk: renesas: Add dummy SDnH clock by Hai Pham · Thu Jan 26 21:01:49 2023 +0100
  11. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  12. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  13. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  14. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  15. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  16. 06c4f9b clk: renesas: Add R8A774A1 clock tables by Adam Ford · Tue Jun 30 09:30:08 2020 -0500
  17. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  18. 69459b2 clk: renesas: Add PE clock handling by Marek Vasut · Thu May 31 19:47:42 2018 +0200
  19. 7ef12c2 clk: renesas: Pull Gen3 specific bits into separate header by Marek Vasut · Mon Jan 08 17:09:45 2018 +0100