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git01.mediatek.com / filogic / uboot / ce1ea41020f6ce223bca8deebe2a79f2d2a409f2 / drivers / ddr / altera / sequencer.c
  1. a321d04 drivers/ddr/altera/sequencer.c: Fix spelling of "resetting". by Vagrant Cascadian · Tue Dec 21 13:07:01 2021 -0800
  2. ed6c1ab ddr: altera: use KBUILD_BASENAME instead of __FILE__ by Marek Vasut · Tue Sep 14 05:20:19 2021 +0200
  3. d3f1735 dm: ddr: socfpga: don't assign values that are not used by Heinrich Schuchardt · Sat Feb 20 10:40:23 2021 +0100
  4. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  5. 6bccacf ddr: altera: Add DDR2 support to Gen5 driver by Marek Vasut · Fri Oct 18 00:22:31 2019 +0200
  6. 2be4a3e dm: ddr: socfpga: fix gen5 ddr driver to not use bss by Simon Goldschmidt · Thu Jul 11 21:18:12 2019 +0200
  7. 24910c3 arm: socfpga: move gen5 SDR driver to DM by Simon Goldschmidt · Tue Apr 16 22:04:39 2019 +0200
  8. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  9. a4af914 ddr: altera: silence PHY calibration unless in debug mode by Goldschmidt Simon · Thu Jan 25 06:04:44 2018 +0000
  10. 66acabc ddr: altera: Repair DQ window centering code by Marek Vasut · Tue Apr 05 23:17:35 2016 +0200
  11. a4b9fa1 ddr: altera: Staticize global variables by Marek Vasut · Tue Apr 05 11:18:38 2016 +0200
  12. 4df2d7b ddr: altera: Make DLEVEL behavior inclusive by Marek Vasut · Mon Apr 04 21:21:05 2016 +0200
  13. f4d3862 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() by Marek Vasut · Mon Apr 04 21:16:18 2016 +0200
  14. 2bf2ee5 ddr: altera: Remove unnecessary ODT mode config by Marek Vasut · Mon Apr 04 19:10:12 2016 +0200
  15. acee8fd ddr: altera: Remove unnecessary update of the SCC by Marek Vasut · Mon Apr 04 18:41:53 2016 +0200
  16. 45ce296 ddr: altera: Fix scc_mgr_set() argument order by Marek Vasut · Mon Apr 04 17:28:16 2016 +0200
  17. 6946989 ddr: altera: Tweak DQS tracking enable handling by Marek Vasut · Tue Apr 05 23:41:56 2016 +0200
  18. 2654bc9 ddr: altera: Replace ad-hoc constant with macro by Marek Vasut · Mon Apr 04 16:07:11 2016 +0200
  19. eb447cb ddr: altera: Repair uninited variable by Marek Vasut · Mon Aug 10 23:01:43 2015 +0200
  20. af67cf3 ddr: altera: Replace float multiplication with integer one by Marek Vasut · Mon Aug 10 22:50:11 2015 +0200
  21. c85b9b3 ddr: altera: sequencer: Clean checkpatch issues by Marek Vasut · Sun Aug 02 19:47:01 2015 +0200
  22. 8af9ca0 ddr: altera: sequencer: Clean data types by Marek Vasut · Sun Aug 02 19:42:26 2015 +0200
  23. 5867376 ddr: altera: sequencer: Pluck out misc macros from code by Marek Vasut · Sun Aug 02 19:26:55 2015 +0200
  24. 324d3f7 ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL by Marek Vasut · Sun Aug 02 19:24:12 2015 +0200
  25. 32d813e ddr: altera: sequencer: Zap VFIFO_SIZE by Marek Vasut · Sun Aug 02 19:21:56 2015 +0200
  26. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · Sun Aug 02 19:18:47 2015 +0200
  27. 7e8f8a7 ddr: altera: sequencer: Pluck out IO_* macros from code by Marek Vasut · Sun Aug 02 19:10:58 2015 +0200
  28. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · Sun Aug 02 19:00:23 2015 +0200
  29. 2dfc76b ddr: altera: sequencer: Pluck out RW_MGR_* macros from code by Marek Vasut · Sun Aug 02 18:44:06 2015 +0200
  30. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · Sun Aug 02 18:12:08 2015 +0200
  31. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · Sun Aug 02 17:15:19 2015 +0200
  32. eb98b38 ddr: altera: sequencer: Zap unused params and macros by Marek Vasut · Sun Aug 02 18:27:21 2015 +0200
  33. 662a8a6 ddr: altera: sequencer: Move qts-generated files to board dir by Marek Vasut · Sun Aug 02 16:55:45 2015 +0200
  34. 98d279a ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 by Marek Vasut · Sun Jul 26 11:46:04 2015 +0200
  35. 7574c87 ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 by Marek Vasut · Sun Jul 26 11:44:54 2015 +0200
  36. 13ee438 ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 by Marek Vasut · Sun Jul 26 11:42:53 2015 +0200
  37. 4b203df ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 by Marek Vasut · Sun Jul 26 11:34:09 2015 +0200
  38. 50d7199 ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 by Marek Vasut · Sun Jul 26 11:11:28 2015 +0200
  39. c140275 ddr: altera: Minor clean up of rw_mgr_mem_handoff() by Marek Vasut · Sun Jul 26 10:59:19 2015 +0200
  40. a358127 ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() by Marek Vasut · Tue Jul 21 06:18:57 2015 +0200
  41. 2da0257 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() by Marek Vasut · Sat Jul 18 05:58:44 2015 +0200
  42. adbaa2d ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() by Marek Vasut · Tue Jul 21 06:00:36 2015 +0200
  43. c67d962 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 by Marek Vasut · Tue Jul 21 05:57:11 2015 +0200
  44. bc773a1 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 by Marek Vasut · Tue Jul 21 05:54:39 2015 +0200
  45. 0b97c42 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1 by Marek Vasut · Tue Jul 21 05:43:37 2015 +0200
  46. 2595b24 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5 by Marek Vasut · Tue Jul 21 05:33:49 2015 +0200
  47. fc2ec8f ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 by Marek Vasut · Tue Jul 21 05:32:49 2015 +0200
  48. 1bb221e ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 by Marek Vasut · Tue Jul 21 05:29:05 2015 +0200
  49. 4e79b0a ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2 by Marek Vasut · Tue Jul 21 05:26:58 2015 +0200
  50. affbc89 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 by Marek Vasut · Tue Jul 21 05:00:42 2015 +0200
  51. 9cdbb96 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11 by Marek Vasut · Tue Jul 21 04:27:32 2015 +0200
  52. d29f804 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10 by Marek Vasut · Sat Jul 18 20:44:28 2015 +0200
  53. dfed1e6 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9 by Marek Vasut · Sat Jul 18 20:42:27 2015 +0200
  54. b69c247 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8 by Marek Vasut · Sat Jul 18 20:34:00 2015 +0200
  55. f1b8f71 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7 by Marek Vasut · Sat Jul 18 19:57:12 2015 +0200
  56. 89feb50 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 by Marek Vasut · Sat Jul 18 19:46:26 2015 +0200
  57. aa0e6e1 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5 by Marek Vasut · Sat Jul 18 19:18:06 2015 +0200
  58. ca8ea37 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4 by Marek Vasut · Sat Jul 18 08:01:45 2015 +0200
  59. 85cd4d7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3 by Marek Vasut · Mon Jul 13 02:48:34 2015 +0200
  60. e624caf ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2 by Marek Vasut · Mon Jul 13 02:38:15 2015 +0200
  61. b20a506 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1 by Marek Vasut · Mon Jul 13 02:11:02 2015 +0200
  62. 4a78cc7 ddr: altera: Clean up rw_mgr_mem_calibrate_writes() by Marek Vasut · Sat Jul 18 07:23:25 2015 +0200
  63. 656002e ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5 by Marek Vasut · Mon Jul 20 03:26:05 2015 +0200
  64. 50a780f ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4 by Marek Vasut · Sun Jul 19 07:57:28 2015 +0200
  65. 28957f3 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3 by Marek Vasut · Sun Jul 19 07:51:17 2015 +0200
  66. c6c1fe7 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2 by Marek Vasut · Sun Jul 19 07:48:58 2015 +0200
  67. a005c77 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1 by Marek Vasut · Sun Jul 19 07:44:21 2015 +0200
  68. a50d5d7 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks() by Marek Vasut · Sun Jul 19 07:35:36 2015 +0200
  69. ec4bbd3 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7 by Marek Vasut · Mon Jul 20 09:11:09 2015 +0200
  70. 28dbf12 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6 by Marek Vasut · Mon Jul 20 09:20:42 2015 +0200
  71. 59729a6 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5 by Marek Vasut · Mon Jul 20 09:20:20 2015 +0200
  72. 6ff36b7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4 by Marek Vasut · Sun Jul 19 07:27:06 2015 +0200
  73. deebda8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 by Marek Vasut · Sun Jul 19 07:03:15 2015 +0200
  74. 970539d ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 by Marek Vasut · Sun Jul 19 07:00:26 2015 +0200
  75. 4896bcc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1 by Marek Vasut · Sun Jul 19 02:42:21 2015 +0200
  76. 088eb21 ddr: altera: Clean up find_vfifo_read() by Marek Vasut · Sun Jul 19 06:45:43 2015 +0200
  77. 42e43ab ddr: altera: Clean up rw_mgr_*_vfifo() part 2 by Marek Vasut · Sun Jul 19 06:37:51 2015 +0200
  78. 1c9f25b ddr: altera: Clean up rw_mgr_*_vfifo() part 1 by Marek Vasut · Sun Jul 19 06:25:27 2015 +0200
  79. 6394ef5 ddr: altera: Clean up sdr_*_phase() part 10 by Marek Vasut · Sun Jul 19 06:04:00 2015 +0200
  80. 6eff803 ddr: altera: Clean up sdr_*_phase() part 9 by Marek Vasut · Sun Jul 19 05:48:30 2015 +0200
  81. f260eec ddr: altera: Clean up sdr_*_phase() part 8 by Marek Vasut · Sun Jul 19 05:42:43 2015 +0200
  82. 2700b9c ddr: altera: Clean up sdr_*_phase() part 7 by Marek Vasut · Sun Jul 19 05:40:06 2015 +0200
  83. 6da8ae4 ddr: altera: Clean up sdr_*_phase() part 6 by Marek Vasut · Sun Jul 19 05:35:40 2015 +0200
  84. f2b02d4 ddr: altera: Clean up sdr_*_phase() part 5 by Marek Vasut · Sun Jul 19 05:26:49 2015 +0200
  85. b148ebe ddr: altera: Clean up sdr_*_phase() part 4 by Marek Vasut · Sun Jul 19 05:01:12 2015 +0200
  86. 434f639 ddr: altera: Clean up sdr_*_phase() part 3 by Marek Vasut · Sun Jul 19 04:37:08 2015 +0200
  87. 6ff1c85 ddr: altera: Clean up sdr_*_phase() part 2 by Marek Vasut · Sun Jul 19 04:34:12 2015 +0200
  88. 139ad79 ddr: altera: Clean up sdr_*_phase() part 1 by Marek Vasut · Sun Jul 19 04:29:21 2015 +0200
  89. fea03c3 ddr: altera: Clean up sdr_find_window_centre() part 3 by Marek Vasut · Sun Jul 19 04:14:32 2015 +0200
  90. ea4c4bb ddr: altera: Clean up sdr_find_window_centre() part 2 by Marek Vasut · Sun Jul 19 04:04:33 2015 +0200
  91. d996e80 ddr: altera: Clean up sdr_find_window_centre() part 1 by Marek Vasut · Sun Jul 19 02:56:59 2015 +0200
  92. 3aa19dc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 by Marek Vasut · Sat Jul 18 04:28:42 2015 +0200
  93. 1beb243 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 by Marek Vasut · Sat Jul 18 04:24:49 2015 +0200
  94. faf820a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 by Marek Vasut · Sat Jul 18 04:20:26 2015 +0200
  95. bb9a5f7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 by Marek Vasut · Sat Jul 18 04:16:45 2015 +0200
  96. 55c4d69 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() by Marek Vasut · Sat Jul 18 03:55:07 2015 +0200
  97. fcef833 ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() by Marek Vasut · Sat Jul 18 03:36:09 2015 +0200
  98. 6a75278 ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup by Marek Vasut · Sat Jul 18 03:34:22 2015 +0200
  99. 349ea3e ddr: altera: Extract Centering DQ/DQS from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 03:10:31 2015 +0200
  100. feb5e65 ddr: altera: Extract DQS enable calibration from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:57:32 2015 +0200