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git01.mediatek.com / filogic / uboot / cc4ecdadec27073a3d6b0a84abbf9f883860ea70 / arch / riscv / cpu / jh7110 / Kconfig
  1. 85621526 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT by Shengyu Qu · Fri Aug 25 00:25:20 2023 +0800
  2. ac4bf43 riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:33 2023 +0800
  3. 8fe34ac riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE by Minda Chen · Mon Aug 07 16:53:37 2023 +0800
  4. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  5. 5203a63 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC by Yanhong Wang · Wed Mar 29 11:42:18 2023 +0800