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git01.mediatek.com / filogic / uboot / c93b518c6366bef07e1311aef2f01b95f14ef8c8 / drivers / clk / clk_zynq.c
  1. 1a3427b clk: treewide: switch to clock dump from clk_ops by Igor Prusov · Thu Nov 09 13:55:15 2023 +0300
  2. b8704af clk: zynq: Move soc_clk_dump to Zynq clock driver by Igor Prusov · Thu Nov 09 13:55:09 2023 +0300
  3. e1c56f3 clk: Add clk_get_by_name_optional by Sean Anderson · Sat Jan 15 15:52:47 2022 -0500
  4. df070ce Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze by Tom Rini · Tue Feb 23 10:45:55 2021 -0500
  5. 4171095 clk: zynq: Add dummy clock enable function by Michal Simek · Tue Feb 09 15:28:15 2021 +0100
  6. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  7. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  8. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  9. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  10. c5d9879 ARM: zynq: Add missing i2c get_rate for fixing i2c SPL by Hannes Schmelzer · Thu Feb 14 08:54:42 2019 +0100
  11. c826a09 clk: Remove DM_FLAG_PRE_RELOC flag in various drivers by Bin Meng · Wed Oct 24 06:36:29 2018 -0700
  12. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  13. 324212d clk: zynq: Show watchdog clock rate properly by Michal Simek · Wed Feb 21 15:06:20 2018 +0100
  14. 2558bff dm: clk: Update uclass to support livetree by Simon Glass · Tue May 30 21:47:29 2017 -0600
  15. 7a49443 dm: core: Replace of_offset with accessor (part 2) by Simon Glass · Wed May 17 17:18:09 2017 -0600
  16. 04f5da9 clk: zynq: Add optional ethernet emio clock source support by Stefan Herbrechtsmeier · Tue Jan 17 16:27:31 2017 +0100
  17. f1f88c9 clk: zynq: Add zynq clock framework driver by Stefan Herbrechtsmeier · Tue Jan 17 16:27:29 2017 +0100