| commit | 324212deb885ec0666fc822d92b54506213e0824 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Wed Feb 21 15:06:20 2018 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Fri Mar 23 09:34:43 2018 +0100 |
| tree | f455d56690cba8e4c9062d55c7b8dce40888d29a | |
| parent | bd307423915448c80482abdd8027a9a3fba05e38 [diff] |
clk: zynq: Show watchdog clock rate properly
watchdog clock is also connected to cpu 1X clocksource.
Zynq> clk dump
...
Before:
swdt 4294967290
After:
swdt 111111110
Signed-off-by: Michal Simek <michal.simek@xilinx.com>