tree f455d56690cba8e4c9062d55c7b8dce40888d29a
parent bd307423915448c80482abdd8027a9a3fba05e38
author Michal Simek <michal.simek@xilinx.com> 1519221980 +0100
committer Michal Simek <michal.simek@xilinx.com> 1521794083 +0100

clk: zynq: Show watchdog clock rate properly

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>