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git01.mediatek.com / filogic / uboot / c7d983a6658d807081ca64eea6fbefaa16c11578 / cpu / mpc85xx
  1. 41a433a ppc/p4080: Fix reporting of PME & FM clock frequencies by Kumar Gala · Wed Dec 09 17:28:17 2009 -0600
  2. 4756ffa ppc/85xx: Map boot page guarded for MP boot by Kumar Gala · Tue Nov 17 20:21:20 2009 -0600
  3. 452ddb6 p4080: add readback to bootpage translation window by Dave Liu · Tue Nov 17 20:01:24 2009 -0600
  4. 419083b ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation by Kumar Gala · Fri Nov 13 09:04:19 2009 -0600
  5. 42f9918 ppc/85xx: Add tracking of TLB CAM usage by Kumar Gala · Thu Nov 12 10:26:16 2009 -0600
  6. b915e0d 85xx: Add support to set DPAA (data path) devices clock frequencies by Kumar Gala · Thu Mar 19 02:46:28 2009 -0500
  7. 8d2817c 85xx: Add support for e500mc cache stashing by Kumar Gala · Thu Mar 19 02:53:01 2009 -0500
  8. 0f602e1 common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL by Heiko Schocher · Thu Dec 03 11:21:21 2009 +0100
  9. c32d80f Merge branch 'master' into next by Wolfgang Denk · Sun Nov 15 23:13:40 2009 +0100
  10. 46ada59 ppc/85xx: make boot from NAND full relocation to RAM by Mingkai Hu · Tue Oct 20 16:58:16 2009 +0800
  11. 7601fb2 ppc/85xx: Fix how we determine the number of CAM entries by Kumar Gala · Fri Nov 13 08:52:21 2009 -0600
  12. b8bb411 ppc/85xx: Fix misc L2 cache enabling bug by Dave Liu · Sat Oct 31 07:59:55 2009 +0800
  13. d61fbcc Coding Style cleanup; update CHANGELOG, prepare -rc1 by Wolfgang Denk · Wed Oct 28 00:49:47 2009 +0100
  14. da22594 mpc85xx: Add eSDHC support for MPC8569E-MDS boards by Anton Vorontsov · Thu Oct 15 17:47:06 2009 +0400
  15. 7feaacb 85xx: MP Boot Page Translation update by Peter Tyser · Fri Oct 23 15:55:47 2009 -0500
  16. 15bf283 ppc/85xx: Fix crashes due to generation of SPE instruction by Leon Woestenberg · Mon Oct 26 10:03:32 2009 +0100
  17. 1721819 ppc/85xx: Make L2 support more robust by Dave Liu · Thu Oct 22 00:10:23 2009 -0500
  18. 4f2fdac relocation: Do not relocate NULL pointers. by Joakim Tjernlund · Thu Oct 08 02:03:51 2009 +0200
  19. 430445f 85xx: Ensure BSS segment isn't linked at address 0 by Peter Tyser · Wed Oct 07 11:45:00 2009 -0500
  20. f48fabc ppc: Enable full relocation to RAM by Peter Tyser · Mon Sep 21 11:20:25 2009 -0500
  21. dccd9e3 ppc/p4080: Determine various chip frequencies on CoreNet platforms by Kumar Gala · Thu Mar 19 02:46:19 2009 -0500
  22. 24f86a8 ppc/p4080: Handle timebase enabling and frequency reporting by Kumar Gala · Thu Sep 17 01:52:37 2009 -0500
  23. bb5409c ppc/p4080: Add various p4080 related defines (and p4040) by Kumar Gala · Thu Mar 19 02:39:17 2009 -0500
  24. 4d9190d ppc/p4080: CoreNet platfrom style secondary core release by Kumar Gala · Thu Sep 17 01:44:39 2009 -0500
  25. a6e7bbf ppc/p4080: CoreNet platfrom style CCSRBAR setting by Kumar Gala · Thu Sep 17 01:44:00 2009 -0500
  26. b6a4090 ppc/85xx: Fix enabling of L2 cache by Kumar Gala · Tue Sep 22 15:45:44 2009 -0500
  27. 780e42b 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ by Vivek Mahajan · Tue Sep 22 12:48:27 2009 +0530
  28. 5fbc7cf ppc/85xx: add cpu init config file for boot from NAND by Mingkai Hu · Tue Sep 22 14:53:21 2009 +0800
  29. 59fd9e2 ppc/85xx: add ld script file for boot from NAND by Mingkai Hu · Tue Sep 22 14:53:10 2009 +0800
  30. 9faa23a ppc/85xx: Disable all async interrupt sources when we boot by Kumar Gala · Fri Sep 11 15:28:41 2009 -0500
  31. 64dd178 ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL by Kumar Gala · Fri Sep 11 13:52:45 2009 -0500
  32. 8aa8cdd ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL by Kumar Gala · Fri Sep 11 13:41:49 2009 -0500
  33. 0255cd7 ppc/85xx: add boot from NAND/eSDHC/eSPI support by Mingkai Hu · Fri Sep 11 14:19:10 2009 +0800
  34. afc51ad ppc/85xx: Move code around to prep for NAND_SPL by Kumar Gala · Fri Sep 11 12:32:01 2009 -0500
  35. f82885e ppc/85xx: Repack tlb_table to save space by Kumar Gala · Fri Sep 11 11:30:30 2009 -0500
  36. c417c91 ppc/85xx: Introduce low level write_tlb function by Kumar Gala · Fri Sep 11 11:27:00 2009 -0500
  37. e957bd7 ppc/85xx: Remove some bogus code from external interrupt handler. by Scott Wood · Thu Aug 20 17:45:00 2009 -0500
  38. 31e6010 ppc/85xx: Ensure that MAS8 is zero when writing TLB entries. by Scott Wood · Thu Aug 20 17:45:05 2009 -0500
  39. 4211596 ppc/85xx: Don't enable interrupts before we're ready by Scott Wood · Thu Aug 20 17:44:20 2009 -0500
  40. 6472af8 ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address by Kumar Gala · Wed Sep 09 11:40:41 2009 -0500
  41. aff0153 ppc/85xx: Clean up do_reset by Kumar Gala · Tue Sep 08 13:46:46 2009 -0500
  42. 36a6843 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). by Poonam Aggrwal · Thu Sep 03 19:42:40 2009 +0530
  43. 4ca72ae ppc/85xx/86xx: Device tree fixup for number of cores by Poonam Aggrwal · Wed Sep 02 19:40:36 2009 +0530
  44. da6e1ca ppc/85xx,86xx: Handling Unknown SOC version by Poonam Aggrwal · Wed Sep 02 13:35:21 2009 +0530
  45. 591ac07 ppc/85xx: Cleanup makefile and related optional files by Kumar Gala · Wed Sep 02 09:00:50 2009 -0500
  46. 8399e12 ppc/85xx: Fix bug in setup_mp code by Kumar Gala · Thu Sep 03 08:41:31 2009 -0500
  47. d13eb3c ppc/85xx: Add a simple function to search the TLB by Kumar Gala · Thu Sep 03 08:20:24 2009 -0500
  48. c24a905 85xx: Add support for setting IVORs to fixed offset defaults by Kumar Gala · Fri Aug 14 13:37:54 2009 -0500
  49. 9387773 ppc/85xx: Fix up eSDHC controller clock frequency in the device tree by Dipen Dudhat · Wed Sep 02 11:25:08 2009 +0530
  50. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  51. 9af188d ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk by Dipen Dudhat · Tue Sep 01 17:27:00 2009 +0530
  52. c5abd7a 85xx: Improve MPIC initialization by Timur Tabi · Thu Aug 20 17:41:11 2009 -0500
  53. 13e21b1 85xx: Added single core members of FSL P1xx/P2xx processors series by Poonam Aggrwal · Thu Aug 20 18:57:45 2009 +0530
  54. d2088e0 85xx: Add L2SRAM Register's macro definition by Mingkai Hu · Tue Aug 18 15:37:15 2009 +0800
  55. 2cca63f 85xx: Move to a common linker script by Kumar Gala · Fri Aug 07 13:00:55 2009 -0500
  56. dfe86a7 85xx: Added P1020 Processor Support. by Poonam Aggrwal · Fri Jul 31 12:08:27 2009 +0530
  57. 4baef82 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx by Poonam Aggrwal · Fri Jul 31 12:08:14 2009 +0530
  58. 9120884 8xxx: Refactored common cpu specific code for 85xx/86xx into one file. by Poonam Aggrwal · Fri Jul 31 12:07:45 2009 +0530
  59. 4c81ed1 85xx: Remove redudant PLATFORM_CPPFLAGS by Kumar Gala · Thu Aug 06 18:28:34 2009 -0500
  60. 6b9b996 Prepare 2009.08-rc3 by Wolfgang Denk · Sat Aug 22 23:27:26 2009 +0200
  61. 87f5792 85xx: Fix addrmap to include memory by Kumar Gala · Fri Aug 14 16:43:22 2009 -0500
  62. 6a6d948 Update Freescale copyrights to remove "All Rights Reserved" by Kumar Gala · Tue Jul 28 21:49:52 2009 -0500
  63. 4e928b5 fsl_dma: Break out common memory initialization function by Peter Tyser · Tue Jun 30 17:15:48 2009 -0500
  64. a9af1dc 8xxx: Move dma_init() call to common code by Peter Tyser · Tue Jun 30 17:15:47 2009 -0500
  65. 4e5649f fsl_dma: Move dma function prototypes to common header file by Peter Tyser · Tue Jun 30 17:15:46 2009 -0500
  66. 86ff89b 8xxx: Rename dma_xfer() to dmacpy() by Peter Tyser · Tue Jun 30 17:15:45 2009 -0500
  67. ae7a7d4 8xxx: Break out DMA code to a common file by Peter Tyser · Tue Jun 30 17:15:40 2009 -0500
  68. 1c9f44e fsl/85xx, 86xx: Sync up DMA code by Peter Tyser · Thu May 21 12:10:00 2009 -0500
  69. 4c82e72 fsl: Create common fsl_dma.h for 85xx and 86xx cpus by Peter Tyser · Thu May 21 12:09:59 2009 -0500
  70. 511d828 qe: Pass in uec_info struct through uec_initialize by Haiying Wang · Thu Jun 04 16:12:41 2009 -0400
  71. 6141468 85xx: Add QE clk support by Haiying Wang · Wed May 20 12:30:29 2009 -0400
  72. a917748 85xx: Added MPC8535/E identifiers by Kumar Gala · Wed May 20 01:11:33 2009 -0500
  73. 47dcd7c 85xx: Always attempt ethernet device tree fixup by Kumar Gala · Thu May 21 08:36:43 2009 -0500
  74. d10d3b1 85xx: Use print_size to report amount of memory not mapped by TLBs by Kumar Gala · Thu Jun 11 23:40:34 2009 -0500
  75. 20db47d 85xx: bugfix for reading maximum TLB size on mpc85xx by Fredrik Arnerup · Tue Jun 02 16:27:10 2009 -0500
  76. e1064b3 85xx: Introduce determine_mp_bootpg() helper. by Kumar Gala · Tue Mar 31 23:11:05 2009 -0500
  77. c984913 MPC85xx: Add MPC8569 CPU support by Haiying Wang · Fri Mar 27 17:02:44 2009 -0400
  78. e56f2c5 85xx: Add support for additional e500mc features by Kumar Gala · Thu Mar 19 09:16:10 2009 -0500
  79. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  80. e674b83 Fix mpc85xx ddr-gen3 ddr_sdram_cfg. by Ed Swarthout · Tue Feb 24 02:37:59 2009 -0600
  81. 1f79d14 Coding style cleanup, update CHANGELOG by Wolfgang Denk · Thu Feb 19 00:41:08 2009 +0100
  82. 6843a6e 85xx: Add eSDHC support for 8536 DS by Andy Fleming · Thu Oct 30 16:51:33 2008 -0500
  83. 30cb145 32bit BUg fix for DDR2 on 8572 by Poonam_Aggrwal-b10812 · Sun Jan 04 08:46:38 2009 +0530
  84. a864f32 mpc85xx: Add support for the P2020 by Srikanth Srinivasan · Wed Jan 21 17:17:33 2009 -0600
  85. 6630ffb 85xx: Fix how we map DDR memory by Kumar Gala · Fri Feb 06 09:56:35 2009 -0600
  86. f92794c 85xx: Format cpu freq printing to handle 8 cores by Kumar Gala · Wed Feb 04 09:35:57 2009 -0600
  87. bb8aea7 Add secondary CPUs processor frequency for e500 core by Haiying Wang · Thu Jan 15 11:58:35 2009 -0500
  88. 64bb6d1 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards by Kumar Gala · Tue Dec 02 16:08:37 2008 -0600
  89. 3fe8087 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards by Kumar Gala · Tue Dec 02 16:08:36 2008 -0600
  90. 8a353d5 Change DDR tlb start entry to CONFIG param for 85xx by Haiying Wang · Tue Jan 13 16:29:22 2009 -0500
  91. 0b691fc mpc8[56]xx: Put localbus clock in sysinfo and gd by Trent Piepho · Wed Dec 03 15:16:37 2008 -0800
  92. a8665ac mpc8568: Double local bus clock divider by Trent Piepho · Wed Dec 03 15:16:35 2008 -0800
  93. 68aec14 85xx: Fix the boot window issue by Dave Liu · Tue Dec 16 12:09:27 2008 +0800
  94. f474551 Set IVPR to kenrel entry point in second core boot page by Haiying Wang · Wed Dec 03 10:08:19 2008 -0500
  95. 1b560ac mpc8xxx: LCRR[CLKDIV] is sometimes five bits by Trent Piepho · Wed Dec 03 15:16:34 2008 -0800
  96. bc424c9 mpc8[56]xx: Put localbus clock in device tree by Trent Piepho · Wed Dec 03 15:16:38 2008 -0800
  97. 9ac287a 85xx: Add support to populate addr map based on TLB settings by Kumar Gala · Tue Dec 16 14:59:20 2008 -0600
  98. 6294850 Update U-Boot's build timestamp on every compile by Peter Tyser · Mon Nov 03 09:30:59 2008 -0600
  99. 629022d 85xx: init gd as early as possible by Kumar Gala · Mon Nov 24 10:29:26 2008 -0600
  100. 7902209 85xx: Fix relocation of CCSRBAR by Kumar Gala · Mon Nov 24 10:29:25 2008 -0600