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git01.mediatek.com / filogic / uboot / c32177d7a28f5ec014582b44cf82af32d05797d8 / arch / riscv / cpu / cpu.c
  1. c32177d riscv: Correct event usage for riscv_cpu_probe/setup by Tom Rini · Mon Sep 04 15:06:35 2023 -0400
  2. f4d52f6 riscv: Rework riscv_cpu_probe for current event macros by Tom Rini · Mon Sep 04 15:06:34 2023 -0400
  3. 69dea21 Merge tag 'v2023.10-rc4' into next by Tom Rini · Mon Sep 04 10:51:58 2023 -0400
  4. b8357c1 event: Convert existing spy records to simple by Simon Glass · Mon Aug 21 21:16:56 2023 -0600
  5. 7ca0dc0 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback by Chanho Park · Fri Aug 18 14:11:03 2023 +0900
  6. 9307401 dm: Emit the arch_cpu_init_dm() even only before relocation by Simon Glass · Thu May 04 16:50:45 2023 -0600
  7. c9382b1 riscv: cpu: check U-Mode before counteren write by Nikita Shubin · Wed Dec 14 08:58:43 2022 +0300
  8. a35afb8 riscv: Fix detecting FPU support in standard extension by Yu Chien Peter Lin · Sat Nov 05 14:02:14 2022 +0800
  9. 9c4d5c1 riscv: Introduce AVAILABLE_HARTS by Rick Chen · Wed Sep 21 14:34:54 2022 +0800
  10. 7e5e029 spl: introduce SPL_XIP to config by Nikita Shubin · Fri Sep 02 11:47:39 2022 +0300
  11. fc55736 event: Convert arch_cpu_init_dm() to use events by Simon Glass · Fri Mar 04 08:43:05 2022 -0700
  12. dc35df4 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · Tue Oct 12 00:00:13 2021 +0300
  13. cc382ff sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · Sun Sep 12 21:11:46 2021 +0200
  14. 4bebdd3 treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · Thu May 20 13:23:52 2021 +0200
  15. 2612080 riscv: cpu: Add callback to init each core by Green Wan · Sun May 02 23:23:04 2021 -0700
  16. dd1cd70 riscv: Clear pending IPIs on initialization by Sean Anderson · Mon Sep 21 07:51:38 2020 -0400
  17. 257875d riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · Sun Jul 19 23:17:07 2020 -0700
  18. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · Wed Jun 24 06:41:19 2020 -0400
  19. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  20. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  21. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  22. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  23. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  24. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · Tue Apr 30 13:49:35 2019 +0800
  25. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  26. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  27. a7544ed riscv: Do some basic architecture level cpu initialization by Bin Meng · Wed Dec 12 06:12:40 2018 -0800
  28. edfe9a9 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · Wed Dec 12 06:12:38 2018 -0800
  29. 2caa1ee riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · Wed Dec 12 06:12:35 2018 -0800
  30. 7a3bbfb riscv: Probe cpus during boot by Bin Meng · Wed Dec 12 06:12:34 2018 -0800
  31. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · Thu Nov 22 11:26:29 2018 +0100
  32. 055700e riscv: Add a helper routine to print CPU information by Bin Meng · Wed Sep 26 06:55:14 2018 -0700