Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b5e687e5de5758e987b49281e464da60a6920899 / arch / riscv / lib / Makefile
  1. 60814cb riscv: Add Zbb support for building U-Boot by Yu Chien Peter Lin · Wed Aug 09 18:49:30 2023 +0800
  2. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  3. c86cb4a arch/riscv: add semihosting support for RISC-V by Kautuk Consul · Wed Dec 07 17:12:35 2022 +0530
  4. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
  5. c39544c riscv: lib: implement enable_caches for sifive cache by Zong Li · Wed Sep 01 15:01:41 2021 +0800
  6. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  7. 369d87a Add support for stack-protector by Joel Peshkin · Sun Apr 11 11:21:58 2021 +0200
  8. 23caf66 riscv: assembler versions of memcpy, memmove, memset by Heinrich Schuchardt · Sat Mar 27 12:37:04 2021 +0100
  9. 5abf1f3 riscv: Move Andes PLMT driver to drivers/timer by Sean Anderson · Sun Oct 25 21:46:56 2020 -0400
  10. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  11. c71f100 riscv: Do not build reset.c if SYSRESET is on by Bin Meng · Mon Jun 22 22:29:44 2020 -0700
  12. 111b804 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · Tue Apr 21 11:15:01 2020 -0700
  13. b161f90 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · Thu Apr 16 08:09:30 2020 -0700
  14. ee3bcd0 riscv: Add basic support for SBI v0.2 by Bin Meng · Mon Mar 09 19:35:28 2020 -0700
  15. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  16. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  17. 583b409 RISCV: image: Add booti support by Atish Patra · Mon May 06 17:49:39 2019 -0700
  18. 7376677 riscv: Add a SYSCON driver for Andestech's PLMT by Rick Chen · Tue Apr 02 15:56:40 2019 +0800
  19. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800
  20. e79178b riscv: implement IPI platform functions using SBI by Lukas Auer · Sun Mar 17 19:28:34 2019 +0100
  21. 83d573d riscv: add infrastructure for calling functions on other harts by Lukas Auer · Sun Mar 17 19:28:32 2019 +0100
  22. f3c8479 riscv: Implement riscv_get_time() API using rdtime instruction by Anup Patel · Wed Dec 12 06:12:31 2018 -0800
  23. b6ee5e1 riscv: Add a SYSCON driver for SiFive's Core Local Interruptor by Bin Meng · Wed Dec 12 06:12:30 2018 -0800
  24. de8d80e riscv: Move do_reset() to a common place by Bin Meng · Wed Sep 26 06:55:22 2018 -0700
  25. 31bdde9 riscv: Add EFI application infrastructure by Alexander Graf · Mon Apr 23 07:59:45 2018 +0200
  26. 3bb8f01 riscv: Add setjmp/longjmp code by Alexander Graf · Mon Apr 23 07:59:43 2018 +0200
  27. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  28. 6eedd92 riscv: nx25: lib: Add relative lib funcs to support RISC-V by Rick Chen · Tue Dec 26 13:55:49 2017 +0800