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git01.mediatek.com / filogic / uboot / b135d93e0daf9598d93cff3c6a9548ff56029903 / cpu / mpc8xxx
  1. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  2. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  3. b834f92 Check DDR interleaving mode by Haiying Wang · 16 years ago
  4. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  5. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  6. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  7. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  8. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  9. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  10. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  11. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago