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git01.mediatek.com / filogic / uboot / ac73f47476abd12c12830c464a096d0313e82d11 / arch / arm / mach-imx / imx8ulp / cgc.c
  1. e9e068f imx: imx8ulp: Update clocks to meet max rate restrictions by Ye Li · Tue Jan 31 16:42:25 2023 +0800
  2. d459ca7 imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers by Ye Li · Tue Jan 31 16:42:21 2023 +0800
  3. 0471ea1 imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init by Ye Li · Wed Apr 06 14:30:14 2022 +0800
  4. 8c0c8d0 imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode by Ye Li · Wed Apr 06 14:30:13 2022 +0800
  5. 4cdb3a3 imx: imx8ulp: add ND/LD clock by Peng Fan · Wed Apr 06 14:30:12 2022 +0800
  6. 8840830 imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock by Ye Li · Fri Oct 29 09:46:30 2021 +0800
  7. da0469d imx8ulp: clock: Support LPAV clocks in cgc and pcc by Ye Li · Fri Oct 29 09:46:18 2021 +0800
  8. 690eea1 arm: imx8ulp: add clock support by Peng Fan · Sat Aug 07 16:00:45 2021 +0800