| commit | d459ca79c21240680fd44963d90c6f9a0091b910 | [log] [tgz] |
|---|---|---|
| author | Ye Li <ye.li@nxp.com> | Tue Jan 31 16:42:21 2023 +0800 |
| committer | Stefano Babic <sbabic@denx.de> | Wed Mar 29 20:15:42 2023 +0200 |
| tree | 531df17303054600555777b003d5c86ac86f3295 | |
| parent | ec7a3853d060fb56bfe9868f71779e2bdcca773a [diff] |
imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>