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git01.mediatek.com / filogic / uboot / aa6e0555069e778326f4ca56d4c9173bf5da5f3b / arch / arm / mach-tegra / tegra210 / clock.c
  1. c226fc7 ARM: tegra: Fix Tegra PWM parent clock by Svyatoslav Ryhel · Tue Feb 14 19:35:28 2023 +0200
  2. 19a5b03 ARM: tegra: clock: add clk_id_to_pll_id helper by Svyatoslav Ryhel · Tue Feb 14 19:35:25 2023 +0200
  3. 7f4ab33 ARM: tegra: remap clock_osc_freq for all Tegra family by Svyatoslav Ryhel · Wed Feb 01 10:53:01 2023 +0200
  4. 47b4c02 doc: replace @return by Return: by Heinrich Schuchardt · Wed Jan 19 18:05:50 2022 +0100
  5. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  6. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  7. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  8. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  9. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  10. 3bb2f5d i2c: t210: Add VI_I2C clock source support by Tom Warren · Fri Mar 27 10:24:31 2020 -0700
  11. f479aca t210: do not enable PLLE and UPHY PLL HW PWRSEQ by JC Kuo · Thu Mar 26 16:10:09 2020 -0700
  12. 58970ae ARM: tegra: Remove disp1 clock initialization on Tegra210 by Thierry Reding · Mon Apr 15 11:32:16 2019 +0200
  13. 317a47c ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210 by Thierry Reding · Mon Apr 15 11:32:15 2019 +0200
  14. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  15. 532543c ARM: tegra: add APIs the clock uclass driver will need by Stephen Warren · Tue Sep 13 10:45:56 2016 -0600
  16. 1453d10 ARM: tegra: add peripheral clock init table by Stephen Warren · Tue Sep 13 10:45:55 2016 -0600
  17. b6409f2 ARM: tegra210: set PLLE_PTS bit when enabling PLLE by Stephen Warren · Tue Mar 22 09:45:36 2016 -0600
  18. 553b61e ARM: tegra210: implement PLLE init procedure from TRM by Stephen Warren · Mon Oct 05 16:58:52 2015 -0600
  19. 4c3aaa7 ARM: tegra: clk_m is the architected timer source clock by Thierry Reding · Thu Aug 20 11:42:20 2015 +0200
  20. fa6e24d ARM: tegra: Implement clk_m by Thierry Reding · Thu Aug 20 11:42:19 2015 +0200
  21. b6ba3fb tegra: Correct logic for reading pll_misc in clock_start_pll() by Simon Glass · Mon Aug 10 07:14:36 2015 -0600
  22. a8480ef Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. by Tom Warren · Thu Jun 25 09:50:44 2015 -0700
  23. 27bce71 Tegra: clocks: Add 38.4MHz OSC support for T210 use by Tom Warren · Mon Jun 22 13:03:44 2015 -0700
  24. f80dd82 ARM: Tegra210: Add SoC code/include files for T210 by Tom Warren · Mon Feb 02 13:22:29 2015 -0700