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git01.mediatek.com / filogic / uboot / a6c078c5b0262834efc67ba6e3b81220e4955fbf / drivers / clk / renesas / r8a77980-cpg-mssr.c
  1. 6f008ee clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:32 2023 +0200
  2. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  3. c3bb162 clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:53 2023 +0100
  4. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  5. 22f9fc7 clk: renesas: Only ever access documented bits in clock driver teardown by Marek Vasut · Sat Apr 25 14:57:45 2020 +0200
  6. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  7. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  8. d52c6cb clk: renesas: Add R8A77980 V3H clock tables by Marek Vasut · Mon Jul 29 19:59:44 2019 +0200