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git01.mediatek.com / filogic / uboot / a6c078c5b0262834efc67ba6e3b81220e4955fbf / drivers / clk / renesas / r8a774e1-cpg-mssr.c
  1. 8319840 clk: renesas: Synchronize RZ R8A774E1 RZ/G2H clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:20 2023 +0100
  2. 436358e clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:41 2023 +0200
  3. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  4. ffdcb5d clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7 by Marek Vasut · Sun Jan 29 02:37:50 2023 +0100
  5. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  6. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  7. eb6474c clk: renesas: Add R8A774E1 clock tables by Biju Das · Wed Oct 14 18:17:36 2020 +0100