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git01.mediatek.com / filogic / uboot / a5a1931ec42d01af6dbb3f431c92123da3801abd / arch / riscv / dts / jh7110-starfive-visionfive-2.dtsi
  1. 1345c9e riscv: dts: jh7110: Add clock source from PLL by Xingyu Wu · Fri Jul 07 18:50:09 2023 +0800
  2. d426942 riscv: dts: starfive: Add support eeprom device tree node by Yanhong Wang · Thu Jun 15 17:36:49 2023 +0800
  3. 7f63bd9 riscv: dts: jh7110: Add ethernet device tree nodes by Yanhong Wang · Thu Jun 15 17:36:44 2023 +0800
  4. 5efc934 riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree by Yanhong Wang · Wed Mar 29 11:42:23 2023 +0800