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git01.mediatek.com / filogic / uboot / a1505dd889a018f53b978f29bb5846a8b3a619e4 / arch / arm / mach-sunxi / dram_sun4i.c
  1. 8dd84a7 sunxi: Move cpu independent code to mach directory by Alexander Graf · Tue Mar 29 17:29:06 2016 +0200[Renamed from arch/arm/cpu/armv7/sunxi/dram_sun4i.c]
  2. ffdc05c sunxi: Make DRAM_ODT_EN Kconfig setting a bool by Hans de Goede · Wed May 13 15:00:46 2015 +0200
  3. 36b2570 sunxi: Move await_completion dram helper to dram.h by Hans de Goede · Mon Dec 08 13:38:21 2014 +0100
  4. ad0dfc5 sun4i: Rename dram_clk_cfg to dram_clk_gate by Hans de Goede · Sun Nov 09 12:24:55 2014 +0100
  5. 5037c45 sun4i: Rename dram files to dram_sun4i.x by Hans de Goede · Sun Nov 02 20:31:16 2014 +0100[Renamed from arch/arm/cpu/armv7/sunxi/dram.c]
  6. 8f32aaa sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I by Ian Campbell · Fri Oct 24 21:20:47 2014 +0100
  7. 05e5bcb sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig option by Hans de Goede · Wed Oct 22 14:56:36 2014 +0200
  8. 1c21155 sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcoding by Hans de Goede · Wed Oct 22 14:48:38 2014 +0200
  9. ea7cdd1 sunxi: dram: Autodetect DDR3 bus width and density by Siarhei Siamashka · Sun Aug 03 05:32:54 2014 +0300
  10. ac7b6fc sunxi: dram: Derive write recovery delay from DRAM clock speed by Siarhei Siamashka · Sun Aug 03 05:32:53 2014 +0300
  11. b41aa97 sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory by Siarhei Siamashka · Sun Aug 03 05:32:52 2014 +0300
  12. b1ace77 sunxi: dram: Configurable DQS gating window mode and delay by Siarhei Siamashka · Sun Aug 03 05:32:51 2014 +0300
  13. c4f0aa5 sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' by Siarhei Siamashka · Sun Aug 03 05:32:50 2014 +0300
  14. 8e9c4fd sunxi: dram: Improve DQS gate data training error handling by Siarhei Siamashka · Sun Aug 03 05:32:49 2014 +0300
  15. 020a634 sunxi: dram: Use divisor P=1 for PLL5 by Siarhei Siamashka · Sun Aug 03 05:32:48 2014 +0300
  16. 586757a sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) by Siarhei Siamashka · Sun Aug 03 05:32:47 2014 +0300
  17. 3ad063a sunxi: dram: Re-introduce the impedance calibration ond ODT by Siarhei Siamashka · Sun Aug 03 05:32:46 2014 +0300
  18. 72ed869 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions by Siarhei Siamashka · Sun Aug 03 05:32:45 2014 +0300
  19. d89297a sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i by Siarhei Siamashka · Sun Aug 03 05:32:44 2014 +0300
  20. 6f66418 sunxi: dram: Remove broken impedance and ODT configuration code by Siarhei Siamashka · Sun Aug 03 05:32:43 2014 +0300
  21. ce4d21c sunxi: dram: Fix CKE delay handling for sun4i/sun5i by Siarhei Siamashka · Sun Aug 03 05:32:42 2014 +0300
  22. a1d9f03 sunxi: dram: Respect the DDR3 reset timing requirements by Siarhei Siamashka · Sun Aug 03 05:32:41 2014 +0300
  23. 551bfb9 sunxi: dram: Remove broken super-standby remnants by Siarhei Siamashka · Sun Aug 03 05:32:40 2014 +0300
  24. 27942f1 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function by Siarhei Siamashka · Sun Aug 03 05:32:39 2014 +0300
  25. 8c1c782 sunxi: Add sun5i support by Hans de Goede · Mon Jun 09 11:36:58 2014 +0200
  26. 3ab9c23 sunxi: Add sun4i support by Hans de Goede · Mon Jun 09 11:36:57 2014 +0200
  27. 2f1afcc sunxi: add sun7i dram setup support by Ian Campbell · Mon May 05 11:52:25 2014 +0100