| commit | ac7b6fcedaba63b73402ad963611111366470f0a | [log] [tgz] |
|---|---|---|
| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | Sun Aug 03 05:32:53 2014 +0300 |
| committer | Hans de Goede <hdegoede@redhat.com> | Tue Aug 12 08:42:33 2014 +0200 |
| tree | bad5641247a95850bc592633bd393d1f690b7c98 | |
| parent | b41aa9710f8a5bb769284c985b812e45c0a5a7b0 [diff] |
sunxi: dram: Derive write recovery delay from DRAM clock speed The write recovery time is 15ns for all JEDEC DDR3 speed bins. And instead of hardcoding it to 10 cycles, it is possible to set tighter timings based on accurate calculations. For example, DRAM clock frequencies up to 533MHz need only 8 cycles for write recovery. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>