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git01.mediatek.com / filogic / uboot / 9e4af83497067b8a055753375f9e69f661fdf495 / arch / x86 / cpu / ivybridge / cpu.c
  1. 9281eb5 x86: ivybridge: Update microcode early in boot by Simon Glass · Thu Jan 01 16:18:14 2015 -0700
  2. 666534f x86: ivybridge: Drop support for ROM caching by Simon Glass · Thu Jan 01 16:18:06 2015 -0700
  3. 642d248 x86: Add post failure codes for bist and car by Bin Meng · Fri Dec 12 21:05:30 2014 +0800
  4. d22f5c9 x86: ivybridge: Add LAPIC support by Simon Glass · Wed Nov 12 22:42:27 2014 -0700
  5. 30580fc x86: ivybridge: Add early init for PCH devices by Simon Glass · Wed Nov 12 22:42:23 2014 -0700
  6. f79d538 x86: ivybridge: Perform Intel microcode update on boot by Simon Glass · Wed Nov 12 22:42:21 2014 -0700
  7. 367077a x86: ivybridge: Check BIST value on boot by Simon Glass · Wed Nov 12 22:42:20 2014 -0700
  8. f226c41 x86: ivybridge: Perform initial CPU setup by Simon Glass · Wed Nov 12 22:42:19 2014 -0700
  9. dcfac35 x86: ivybridge: Add early LPC init so that serial works by Simon Glass · Wed Nov 12 22:42:15 2014 -0700
  10. 3274ae0 x86: ivybridge: Enable PCI in early init by Simon Glass · Wed Nov 12 22:42:13 2014 -0700
  11. 98f139b x86: chromebook_link: Implement CAR support (cache as RAM) by Simon Glass · Wed Nov 12 22:42:10 2014 -0700
  12. 0b36ecd x86: Add chromebook_link board by Simon Glass · Wed Nov 12 22:42:07 2014 -0700