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git01.mediatek.com / filogic / uboot / 9d70c9c7a9bf21bc2f00fe8c9a7298826bea1cf9 / drivers / clk / clk-hsdk-cgu.c
  1. 9d70c9c CLK: HSDK: Check for PLL bypass firstly by Eugeniy Paltsev · 4 years, 10 months ago
  2. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · 7 years ago
  3. 7d7d9f2 ARC: HSDK: CGU: Add 'Hz' when printing clock frequency by Eugeniy Paltsev · 7 years ago
  4. a5a238f ARC: HSDK: CGU: Use plat data instead of priv data by Eugeniy Paltsev · 7 years ago
  5. 7451424 ARC: HSDK: CGU: Update AXI, TUN, ARC clock options by Eugeniy Paltsev · 7 years ago
  6. 7e1fb09 ARC: clk: introduce HSDK CGU clock driver by Eugeniy Paltsev · 7 years ago