| commit | 7451424863500440f85dbae61d62665408619621 | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Tue Jan 16 20:44:25 2018 +0300 |
| committer | Alexey Brodkin <abrodkin@synopsys.com> | Fri Jan 19 17:59:35 2018 +0300 |
| tree | 7d10db927078e61b2b4b718ee18cdbc521b73e66 | |
| parent | 3bc276a3ee76602030b6bb134b443a9eabe34f57 [diff] |
ARC: HSDK: CGU: Update AXI, TUN, ARC clock options Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>