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git01.mediatek.com / filogic / uboot / 92007cfbe206a69eaecd4dd74cee0c2ecd3be69e / drivers / clk / clk-hsdk-cgu.c
  1. 6575713 ARC: HSDK: CGU: add support for timer clock by Eugeniy Paltsev · Thu Apr 23 14:50:50 2020 +0300
  2. c6f15de ARC: HSDK: CGU: fix tunnel clock calculation by Eugeniy Paltsev · Thu Apr 16 22:35:11 2020 +0300
  3. 5872fc6 CLK: HSDK: fix HDMI clock calculation by Eugeniy Paltsev · Wed Jan 29 14:08:30 2020 +0300
  4. 9d70c9c CLK: HSDK: Check for PLL bypass firstly by Eugeniy Paltsev · Wed Jan 29 14:08:29 2020 +0300
  5. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · Wed Apr 18 13:50:47 2018 -0400
  6. 7d7d9f2 ARC: HSDK: CGU: Add 'Hz' when printing clock frequency by Eugeniy Paltsev · Tue Jan 16 20:44:27 2018 +0300
  7. a5a238f ARC: HSDK: CGU: Use plat data instead of priv data by Eugeniy Paltsev · Tue Jan 16 20:44:26 2018 +0300
  8. 7451424 ARC: HSDK: CGU: Update AXI, TUN, ARC clock options by Eugeniy Paltsev · Tue Jan 16 20:44:25 2018 +0300
  9. 7e1fb09 ARC: clk: introduce HSDK CGU clock driver by Eugeniy Paltsev · Sun Dec 10 21:20:08 2017 +0300