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git01.mediatek.com / filogic / uboot / 87e4f18ff34f11073d4f9b50768428b9c446b70d / drivers / clk / mvebu
  1. 9c75dd1 clk: armada-37xx-periph: fix DDR PHY clock divider values by Marek Behún · Wed Apr 15 00:59:18 2020 +0200
  2. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  3. 7bafd04 clk: armada-37xx-periph: Support changing clock parent and rate by Marek Behún · Fri Aug 17 12:58:52 2018 +0200
  4. d8e6942 clk: armada-37xx: Support soc_clk_dump by Marek Behún · Tue Apr 24 17:21:27 2018 +0200
  5. 61d74e8 driver: clk: Add support for clocks on Armada 37xx by Marek Behún · Tue Apr 24 17:21:25 2018 +0200