| commit | 9c75dd1df7cd412cde1eb160145f53c96bb7840e | [log] [tgz] |
|---|---|---|
| author | Marek Behún <marek.behun@nic.cz> | Wed Apr 15 00:59:18 2020 +0200 |
| committer | Stefan Roese <sr@denx.de> | Wed Apr 22 14:28:15 2020 +0200 |
| tree | 03d98bd80c8bde4f47f41a6d78a85494c081f5e0 | |
| parent | a473057268d9e0b13ed7754f6fa9ab731fe4878c [diff] |
clk: armada-37xx-periph: fix DDR PHY clock divider values Register value table for DDR PHY clock divider are wrong. They should be 0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current values do not make sense, since 2 cannot be achieved, because the register is only 1 bit long (mask is set to 1). This fixes clk dump reporting DDR PHY clock rate differently from Linux. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>