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git01.mediatek.com / filogic / uboot / 70848515fbfaf25b806b3bde9b936d8cd9656cd0 / drivers / clk / clk_zynq.c
  1. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  2. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  3. c5d9879 ARM: zynq: Add missing i2c get_rate for fixing i2c SPL by Hannes Schmelzer · Thu Feb 14 08:54:42 2019 +0100
  4. c826a09 clk: Remove DM_FLAG_PRE_RELOC flag in various drivers by Bin Meng · Wed Oct 24 06:36:29 2018 -0700
  5. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  6. 324212d clk: zynq: Show watchdog clock rate properly by Michal Simek · Wed Feb 21 15:06:20 2018 +0100
  7. 2558bff dm: clk: Update uclass to support livetree by Simon Glass · Tue May 30 21:47:29 2017 -0600
  8. 7a49443 dm: core: Replace of_offset with accessor (part 2) by Simon Glass · Wed May 17 17:18:09 2017 -0600
  9. 04f5da9 clk: zynq: Add optional ethernet emio clock source support by Stefan Herbrechtsmeier · Tue Jan 17 16:27:31 2017 +0100
  10. f1f88c9 clk: zynq: Add zynq clock framework driver by Stefan Herbrechtsmeier · Tue Jan 17 16:27:29 2017 +0100