Log - 6df28ed9622122bdaf4d646401ea9eee5d9e272f - filogic/uboot

553b61e ARM: tegra210: implement PLLE init procedure from TRM by Stephen Warren · Mon Oct 05 16:58:52 2015 -0600
4c3aaa7 ARM: tegra: clk_m is the architected timer source clock by Thierry Reding · Thu Aug 20 11:42:20 2015 +0200
fa6e24d ARM: tegra: Implement clk_m by Thierry Reding · Thu Aug 20 11:42:19 2015 +0200
b6ba3fb tegra: Correct logic for reading pll_misc in clock_start_pll() by Simon Glass · Mon Aug 10 07:14:36 2015 -0600
a8480ef Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. by Tom Warren · Thu Jun 25 09:50:44 2015 -0700
27bce71 Tegra: clocks: Add 38.4MHz OSC support for T210 use by Tom Warren · Mon Jun 22 13:03:44 2015 -0700
f80dd82 ARM: Tegra210: Add SoC code/include files for T210 by Tom Warren · Mon Feb 02 13:22:29 2015 -0700