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git01.mediatek.com / filogic / uboot / 60ff464d8806c8fde4c13091b5bf3f348fd63f18 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  2. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  3. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  4. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago