Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
uboot
/
5abfb13628b4e20a6828c5ace41ee3675ba016a0
/
arch
/
riscv
/
cpu
842d580
riscv: cache: Implement i/dcache [status, enable, disable]
by Rick Chen
· Wed Nov 07 09:34:06 2018 +0800
39a652b
riscv: save hart ID and device tree passed by prior boot stage
by Lukas Auer
· Thu Nov 22 11:26:29 2018 +0100
8598e6b
riscv: do not blindly modify the mstatus CSR
by Lukas Auer
· Thu Nov 22 11:26:28 2018 +0100
230ab8a
riscv: remove unused labels in start.S
by Lukas Auer
· Thu Nov 22 11:26:27 2018 +0100
ccd035a
Drop CONFIG_INIT_CRITICAL
by Bin Meng
· Thu Nov 22 11:26:26 2018 +0100
af51285
riscv: align mtvec on a 4-byte boundary
by Lukas Auer
· Thu Nov 22 11:26:25 2018 +0100
7cf4368
riscv: fix inconsistent use of spaces and tabs in start.S
by Lukas Auer
· Thu Nov 22 11:26:24 2018 +0100
de8d80e
riscv: Move do_reset() to a common place
by Bin Meng
· Wed Sep 26 06:55:22 2018 -0700
8a8694d
riscv: Add QEMU virt board support
by Bin Meng
· Wed Sep 26 06:55:21 2018 -0700
bcb3843
riscv: Make start.S available for all targets
by Bin Meng
· Wed Sep 26 06:55:17 2018 -0700
055700e
riscv: Add a helper routine to print CPU information
by Bin Meng
· Wed Sep 26 06:55:14 2018 -0700
c7feb19
riscv: Fix coding style issues in the linker script
by Bin Meng
· Wed Sep 26 06:55:12 2018 -0700
a28e0f5
riscv: Move the linker script to the CPU root directory
by Bin Meng
· Wed Sep 26 06:55:11 2018 -0700
b28f7b3
riscv: Include bss subsections in linker script
by Alexander Graf
· Mon Aug 20 14:25:49 2018 +0200
94a10f2
efi_loader: Rename sections to allow for implicit data
by Alexander Graf
· Tue Jun 12 07:48:37 2018 +0200
b66af37
riscv: cpu: nx25: Rename as ax25
by Rick Chen
· Tue May 29 09:54:40 2018 +0800
9677a37
efi_loader: Enable RISC-V support
by Rick Chen
· Mon May 28 19:06:37 2018 +0800
10e4779
SPDX: Convert all of our single license tags to Linux Kernel style
by Tom Rini
· Sun May 06 17:58:06 2018 -0400
40a6fe7
riscv: ae250: Support DT provided by the board at runtime
by Rick Chen
· Thu Mar 29 10:08:33 2018 +0800
e76b804
riscv: cpu: Add nx25 to support RISC-V
by Rick Chen
· Tue Dec 26 13:55:48 2017 +0800