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git01.mediatek.com
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filogic
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uboot
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58a412ea369359f4530e9e4b9faa4b6c06b7467f
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arch
/
riscv
/
lib
922eec0
riscv: andes: Fix enable register settings of PLICSW
by Yu Chien Peter Lin
· Thu Nov 16 20:46:12 2023 +0800
8bf50cd
riscv: allow resume after exception
by Heinrich Schuchardt
· Tue Oct 31 14:55:51 2023 +0200
ac1c3d0
riscv: Weakly define invalidate_icache_range()
by Samuel Holland
· Tue Oct 31 00:37:20 2023 -0500
b6b9900
riscv: Remove common.h usage
by Tom Rini
· Thu Oct 12 19:03:59 2023 -0400
60814cb
riscv: Add Zbb support for building U-Boot
by Yu Chien Peter Lin
· Wed Aug 09 18:49:30 2023 +0800
1a9a7a9
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy
by Randolph
· Thu Oct 12 13:35:34 2023 +0800
19f6361
riscv: bootstage: correct bootstage_report guard
by Chanho Park
· Wed Sep 06 14:18:12 2023 +0900
b29a747
Merge branch 'next'
by Tom Rini
· Mon Oct 02 10:55:44 2023 -0400
bdd5f81
common: Drop linux/printk.h from common header
by Simon Glass
· Thu Sep 14 18:21:46 2023 -0600
a7289b6
risc-v: implement DBCN write byte
by Heinrich Schuchardt
· Mon Sep 04 13:24:03 2023 +0200
b8357c1
event: Convert existing spy records to simple
by Simon Glass
· Mon Aug 21 21:16:56 2023 -0600
b5f0372
riscv: Rename SiFive CLINT to RISC-V ALINT
by Bin Meng
· Wed Jun 21 23:11:46 2023 +0800
08b8d26
riscv: clint: Update the sifive clint ipi driver to support aclint
by Bin Meng
· Wed Jun 21 23:11:45 2023 +0800
c99c384
riscv: andes_plicsw: Fix IPI during OpenSBI invocation
by Yu Chien Peter Lin
· Tue Jul 04 19:13:20 2023 +0800
c34de68
riscv: semihosting: replace inline assembly with assembly file
by Andre Przywara
· Tue Feb 07 15:21:05 2023 +0000
ae7ed57
Correct SPL uses of LMB
by Simon Glass
· Sun Feb 05 15:40:13 2023 -0700
718e569
riscv: memcpy: check src and dst before copy
by Rick Chen
· Wed Jan 04 09:56:28 2023 +0800
e84ab96
efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE
by Heinrich Schuchardt
· Fri Dec 23 02:16:03 2022 +0100
c86cb4a
arch/riscv: add semihosting support for RISC-V
by Kautuk Consul
· Wed Dec 07 17:12:35 2022 +0530
739cd6f
riscv: Rename Andes PLIC to PLICSW
by Yu Chien Peter Lin
· Tue Oct 25 23:03:50 2022 +0800
bcb208b
riscv: andes_plic.c: use modified IPI scheme
by Yu Chien Peter Lin
· Fri Oct 14 15:00:18 2022 +0800
2e4938b
dm: core: Drop ofnode_is_available()
by Simon Glass
· Tue Sep 06 20:27:17 2022 -0600
df00afa
treewide: Drop bootm_headers_t typedef
by Simon Glass
· Tue Sep 06 20:26:50 2022 -0600
9c4d5c1
riscv: Introduce AVAILABLE_HARTS
by Rick Chen
· Wed Sep 21 14:34:54 2022 +0800
7e5e029
spl: introduce SPL_XIP to config
by Nikita Shubin
· Fri Sep 02 11:47:39 2022 +0300
8aaae3d
zynqmp: Run board_get_usable_ram_top() only on main U-Boot
by Ashok Reddy Soma
· Thu Jul 07 10:45:37 2022 +0200
c65d29f
arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED
by Michal Simek
· Thu Jul 07 10:47:16 2022 +0200
f4b4d75
riscv: provide missing base extension functions
by Heinrich Schuchardt
· Thu Mar 17 07:36:14 2022 +0100
fc55736
event: Convert arch_cpu_init_dm() to use events
by Simon Glass
· Fri Mar 04 08:43:05 2022 -0700
f263479
efi_loader: fix SectionAlignment, FileAlignment
by Heinrich Schuchardt
· Fri Jan 14 21:40:15 2022 +0100
f0106d4
riscv: revert Complete efi header for RV32/64
by Heinrich Schuchardt
· Sun Jan 09 18:16:11 2022 +0100
69c681e
riscv: function to retrieve SBI implementation version
by Heinrich Schuchardt
· Mon Oct 25 15:09:34 2021 +0200
bedc439
fdtdec: Support reserved-memory flags
by Thierry Reding
· Fri Sep 03 15:16:21 2021 +0200
5e33691
fdtdec: Support compatible string list for reserved memory
by Thierry Reding
· Fri Sep 03 15:16:19 2021 +0200
85c057e
image: Drop IMAGE_ENABLE_OF_LIBFDT
by Simon Glass
· Sat Sep 25 19:43:21 2021 -0600
cc382ff
sysreset: provide SBI based sysreset driver
by Heinrich Schuchardt
· Sun Sep 12 21:11:46 2021 +0200
c7ad952
riscv: Fix setting no-map in reserved memory nodes
by Samuel Holland
· Sun Sep 12 11:05:47 2021 -0500
637fa28
lmb: riscv: Add arch_lmb_reserve()
by Marek Vasut
· Fri Sep 10 22:47:15 2021 +0200
c39544c
riscv: lib: implement enable_caches for sifive cache
by Zong Li
· Wed Sep 01 15:01:41 2021 +0800
a33070c
common: board_r: support enable_caches for RISC-V
by Zong Li
· Wed Sep 01 15:01:40 2021 +0800
79c6855
riscv: show code leading to exception
by Heinrich Schuchardt
· Sat Sep 04 10:36:49 2021 +0200
5629aaa
efi_loader: add Linux magic to RISC-V crt0
by Heinrich Schuchardt
· Fri May 28 22:24:37 2021 +0200
51744fe
riscv: booti: do not force relocation if force_reloc is not set
by Vitaly Wool
· Tue Apr 06 10:50:16 2021 +0300
b6ec26b
riscv: andes_plic: Fix riscv_get_ipi() mask
by Bin Meng
· Tue Jun 15 13:45:57 2021 +0800
442d446
riscv: Drop USE_SPL_FIT_GENERATOR
by Bin Meng
· Mon May 10 20:23:41 2021 +0800
8a27fcd
riscv: Fix memmove and optimise memcpy when misalign
by Bin Meng
· Thu May 13 16:46:17 2021 +0800
ac95f46
riscv: Fix arch_fixup_fdt always failing without /chosen
by Sean Anderson
· Fri May 14 22:36:16 2021 -0400
614b1d8
riscv: Split SiFive CLINT support between SPL and U-Boot proper
by Bin Meng
· Tue May 11 20:04:12 2021 +0800
369d87a
Add support for stack-protector
by Joel Peshkin
· Sun Apr 11 11:21:58 2021 +0200
23caf66
riscv: assembler versions of memcpy, memmove, memset
by Heinrich Schuchardt
· Sat Mar 27 12:37:04 2021 +0100
76eb648
riscv: simplify longjmp
by Heinrich Schuchardt
· Tue Mar 23 19:11:26 2021 +0100
3ba929a
common: Drop asm/global_data.h from common header
by Simon Glass
· Fri Oct 30 21:38:53 2020 -0600
bb721de
Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next
by Tom Rini
· Tue Jan 05 22:34:43 2021 -0500
65130cd
dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
by Simon Glass
· Mon Dec 28 20:34:56 2020 -0700
dd5d79b
riscv: Complete efi header for RV32/64
by Leo Yu-Chi Liang
· Mon Nov 16 17:07:41 2020 +0800
b68402d
riscv: Fix efi header size for RV32
by Leo Yu-Chi Liang
· Thu Nov 12 10:09:52 2020 +0800
fa36696
riscv: Fix efi header for RV32
by Atish Patra
· Tue Oct 13 12:23:31 2020 -0700
b881ba8
riscv: reset after crash
by Heinrich Schuchardt
· Wed Dec 02 14:36:26 2020 +0100
52a1db7
riscv: Move timer portions of SiFive CLINT to drivers/timer
by Sean Anderson
· Sun Oct 25 21:46:58 2020 -0400
5abf1f3
riscv: Move Andes PLMT driver to drivers/timer
by Sean Anderson
· Sun Oct 25 21:46:56 2020 -0400
947fc2d
timer: Return count from timer_ops.get_count
by Sean Anderson
· Wed Oct 07 14:37:44 2020 -0400
38ae92e
Merge branch 'next'
by Tom Rini
· Mon Oct 05 13:05:46 2020 -0400
2c4c7d1
riscv: Ensure gp is NULL or points to valid data
by Sean Anderson
· Mon Sep 21 07:51:40 2020 -0400
ff184fe
riscv: Use a valid bit to ignore already-pending IPIs
by Sean Anderson
· Mon Sep 21 07:51:37 2020 -0400
cfb0809
riscv: Match memory barriers between send_ipi_many and handle_ipi
by Sean Anderson
· Mon Sep 21 07:51:36 2020 -0400
272ab20
riscv: Rework Sifive CLINT as UCLASS_TIMER driver
by Sean Anderson
· Mon Sep 28 10:52:26 2020 -0400
28bfc32
riscv: Clean up initialization in Andes PLIC
by Sean Anderson
· Mon Sep 28 10:52:25 2020 -0400
87e6ce5
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
by Sean Anderson
· Mon Sep 28 10:52:24 2020 -0400
9baaaef
riscv: Rework riscv timer driver to only support S-mode
by Sean Anderson
· Mon Sep 28 10:52:21 2020 -0400
fbef54d
riscv: restore global data pointer in trap handler
by Heinrich Schuchardt
· Sat Sep 26 07:50:36 2020 +0200
646f8c6
fdtdec: optionally add property no-map to created reserved memory node
by Etienne Carriere
· Thu Sep 10 10:49:59 2020 +0200
95492ae
cmd: provide command sbi
by Heinrich Schuchardt
· Thu Aug 20 19:43:39 2020 +0200
c78eef7
riscv: fix building with CONFIG_SPL_SMP=n
by Heinrich Schuchardt
· Sat Aug 15 09:49:26 2020 +0200
77efe24
riscv: additional crash information
by Heinrich Schuchardt
· Sat Aug 01 15:15:39 2020 +0000
d2014d1
riscv: remove redundant logical constraint.
by Heinrich Schuchardt
· Mon Aug 03 23:33:42 2020 +0200
63dcfcb
riscv: Call spl_board_init_f() in the generic SPL board_init_f()
by Bin Meng
· Sun Aug 02 23:09:01 2020 -0700
3af8678
Revert "riscv: Allow use of reset drivers"
by Bin Meng
· Sun Jul 19 20:06:45 2020 -0700
257875d
riscv: Make SiFive HiFive Unleashed board boot again
by Bin Meng
· Sun Jul 19 23:17:07 2020 -0700
90fa4e9
Merge branch 'next'
by Tom Rini
· Mon Jul 06 15:46:38 2020 -0400
8cfbea0
riscv: use log functions in fdt_fixup
by Heinrich Schuchardt
· Tue Jun 30 11:30:59 2020 +0200
491734f
riscv: Use optimized version of fdtdec_get_addr_size_no_parent
by Atish Patra
· Wed Jun 24 14:56:15 2020 -0700
f0947db
riscv: Do not return error if reserved node already exists
by Atish Patra
· Wed Jun 24 14:56:14 2020 -0700
c71f100
riscv: Do not build reset.c if SYSRESET is on
by Bin Meng
· Mon Jun 22 22:29:44 2020 -0700
7a36bd8
riscv: Expand the DT size before copy reserved memory node
by Bin Meng
· Thu Jun 25 18:16:07 2020 -0700
77073f4
riscv: Avoid the reserved memory fixup if src and dst point to the same place
by Bin Meng
· Thu Jun 25 18:16:06 2020 -0700
35e14fb
riscv: Allow use of reset drivers
by Sean Anderson
· Wed Jun 24 06:41:20 2020 -0400
b1d0cb3
riscv: Clean up IPI initialization code
by Sean Anderson
· Wed Jun 24 06:41:18 2020 -0400
e622c74
riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01
by Bin Meng
· Wed May 27 02:04:53 2020 -0700
b391ead
riscv: sbi: Remove sbi_spec_version
by Bin Meng
· Wed May 27 02:04:52 2020 -0700
a7edd07
riscv: Move all SMP related SBI calls to SBI_v01
by Atish Patra
· Tue Apr 21 14:51:57 2020 -0700
0f2af88
common: Drop log.h from common header
by Simon Glass
· Sun May 10 11:40:05 2020 -0600
ed38aef
command: Remove the cmd_tbl_t typedef
by Simon Glass
· Sun May 10 11:40:03 2020 -0600
9758973
common: Drop init.h from common header
by Simon Glass
· Sun May 10 11:40:02 2020 -0600
2dc9c34
common: Drop image.h from common header
by Simon Glass
· Sun May 10 11:40:01 2020 -0600
1ea9789
common: Drop bootstage.h from common header
by Simon Glass
· Sun May 10 11:40:00 2020 -0600
82ed8ef
riscv: Move all fdt fixups together
by Atish Patra
· Tue Apr 21 11:15:04 2020 -0700
5fbac33
riscv: Copy the reserved-memory nodes to final DT
by Atish Patra
· Tue Apr 21 11:15:03 2020 -0700
7379192
riscv: Setup reserved-memory node for FU540
by Atish Patra
· Tue Apr 21 11:15:02 2020 -0700
111b804
riscv: Provide a mechanism to fix DT for reserved memory
by Atish Patra
· Tue Apr 21 11:15:01 2020 -0700
af3c043
riscv: Add boot hartid to device tree
by Atish Patra
· Tue Apr 21 11:14:59 2020 -0700
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