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git01.mediatek.com / filogic / uboot / 541f62c2f923a1ae4b182ce19d45830154f7e264 / drivers / serial / serial_sifive.c
  1. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  2. aad29ae dm: treewide: Rename ofdata_to_platdata() to of_to_plat() by Simon Glass · Thu Dec 03 16:55:21 2020 -0700
  3. fa20e93 dm: treewide: Rename dev_get_platdata() to dev_get_plat() by Simon Glass · Thu Dec 03 16:55:20 2020 -0700
  4. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  5. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  6. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  7. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  8. 024d060 riscv : serial: use rx watermark to indicate rx data is present by Sagar Shrikant Kadam · Tue Jul 09 05:23:44 2019 -0700
  9. 9ee724f serial: sifive: Change include order by Jagan Teki · Wed May 08 19:56:16 2019 +0530
  10. 574fa69 drivers: serial_sifive: Skip baudrate config if no input clock by Atish Patra · Mon Feb 25 08:15:08 2019 +0000
  11. bc922d4 drivers: serial_sifive: Fix baud rate calculation by Atish Patra · Mon Feb 25 08:15:02 2019 +0000
  12. 4b1d68f drivers: serial: Add SiFive UART driver by Anup Patel · Sat Dec 15 11:35:15 2018 +0530