| commit | 4b1d68f8c63820df50c184e924028d71748f3da9 | [log] [tgz] |
|---|---|---|
| author | Anup Patel <anup@brainfault.org> | Sat Dec 15 11:35:15 2018 +0530 |
| committer | Andes <uboot@andestech.com> | Tue Dec 18 09:56:54 2018 +0800 |
| tree | 327ef0a22123e963b4f7e0a2bfe3695a49ff2187 | |
| parent | f331b9b707d5fde0b94f9c78bda1ff7065cd488a [diff] |
drivers: serial: Add SiFive UART driver This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>