Log - 4cac2e06d29cf819dc2b7b6d74461df0ea346921 - filogic/uboot

e4bfc44 clk: mediatek: mt7988: rename CK to CLK by Christian Marangi · Sat Aug 03 10:33:02 2024 +0200
826afb7 clk: mediatek: mt7988: convert to unified infracfg gates + muxes by Christian Marangi · Sat Aug 03 10:33:01 2024 +0200
54894b3 clk: mediatek: mt7988: replace clock ID with upstream linux by Christian Marangi · Sat Aug 03 10:33:00 2024 +0200
dee002c clk: mediatek: mt7988: comment out infracfg clk not defined by Christian Marangi · Sat Aug 03 10:32:59 2024 +0200
245c850 clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen by Christian Marangi · Sat Aug 03 10:32:58 2024 +0200
ecf47ee clk: mediatek: mt7988: reorder TOPCKGEN factor ID by Christian Marangi · Sat Aug 03 10:32:57 2024 +0200
532f979 clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming by Christian Marangi · Sat Aug 03 10:32:56 2024 +0200
d1f073e clk: mediatek: mt7988: drop 1/1 infracfg spurious factor by Christian Marangi · Sat Aug 03 10:32:55 2024 +0200
70bc4e4 clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 by Christian Marangi · Sat Aug 03 10:32:54 2024 +0200
82a4ce2 clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top by Christian Marangi · Sat Aug 03 10:32:53 2024 +0200
fb43efd clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL by Christian Marangi · Sat Aug 03 10:32:52 2024 +0200
6db498a clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL by Christian Marangi · Sat Aug 03 10:32:51 2024 +0200
2861be6 clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL by Christian Marangi · Sat Aug 03 10:32:50 2024 +0200
b25423f clk: mediatek: mt7988: support alternative compatible for fixed-plls by Christian Marangi · Mon Jun 24 23:03:39 2024 +0200
d27e302 clk: mediatek: add clock driver support for MediaTek MT7988 SoC by developer · Wed Jul 19 17:16:28 2023 +0800