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git01.mediatek.com / filogic / uboot / 41710952b68960a2dbdbbd96403891f2e2aa4622 / drivers / clk / clk_zynq.c
  1. 4171095 clk: zynq: Add dummy clock enable function by Michal Simek · 3 years, 10 months ago
  2. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · 4 years ago
  3. 0f2af88 common: Drop log.h from common header by Simon Glass · 4 years, 7 months ago
  4. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · 4 years, 10 months ago
  5. c5d9879 ARM: zynq: Add missing i2c get_rate for fixing i2c SPL by Hannes Schmelzer · 6 years ago
  6. c826a09 clk: Remove DM_FLAG_PRE_RELOC flag in various drivers by Bin Meng · 6 years ago
  7. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
  8. 324212d clk: zynq: Show watchdog clock rate properly by Michal Simek · 7 years ago
  9. 2558bff dm: clk: Update uclass to support livetree by Simon Glass · 7 years ago
  10. 7a49443 dm: core: Replace of_offset with accessor (part 2) by Simon Glass · 8 years ago
  11. 04f5da9 clk: zynq: Add optional ethernet emio clock source support by Stefan Herbrechtsmeier · 8 years ago
  12. f1f88c9 clk: zynq: Add zynq clock framework driver by Stefan Herbrechtsmeier · 8 years ago