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git01.mediatek.com / filogic / uboot / 4061aa1b964a48fa2839f015dc1c6de6602dfd68 / board / freescale / mx7ulp_evk / plugin.S
  1. 79d3f92 mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0 by Ye Li · Wed May 15 09:57:01 2019 +0000
  2. 15c8093 mx7ulp: Select the SCG1 APLL PFD as a system clock source by Ye Li · Wed May 15 09:56:59 2019 +0000
  3. 87cff10 mx7ulp_evk: Change APLL and its PFD0 frequencies by Ye Li · Wed May 15 09:56:56 2019 +0000
  4. 2ed2ecc mx7ulp_evk: Update LPDDR3 script by Ye Li · Wed May 15 09:56:53 2019 +0000
  5. 8fb2792 mx7ulp: Fix APLL num and denom setting issue by Ye Li · Wed May 15 09:56:51 2019 +0000
  6. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  7. f7765d7 imx: imx7ulp: add EVK board support by Peng Fan · Wed Feb 22 16:21:56 2017 +0800