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git01.mediatek.com / filogic / uboot / 3a21671194ef8f7bd0c3d722ddcd5fc534d816a6 / drivers / clk / renesas / rcar-gen3-cpg.h
  1. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  2. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  3. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  4. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  5. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  6. 06c4f9b clk: renesas: Add R8A774A1 clock tables by Adam Ford · Tue Jun 30 09:30:08 2020 -0500
  7. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  8. 69459b2 clk: renesas: Add PE clock handling by Marek Vasut · Thu May 31 19:47:42 2018 +0200
  9. 7ef12c2 clk: renesas: Pull Gen3 specific bits into separate header by Marek Vasut · Mon Jan 08 17:09:45 2018 +0100