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git01.mediatek.com / filogic / uboot / 33651ac605fdbf6f31f432e8b7b3967adf87973c / include / fsl_ddr.h
  1. d259d9c global: Remove unused CONFIG defines by Tom Rini · Tue Jan 10 11:19:28 2023 -0500
  2. f839dd0 Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig by Tom Rini · Sun Jul 31 21:08:22 2022 -0400
  3. ed38aef command: Remove the cmd_tbl_t typedef by Simon Glass · Sun May 10 11:40:03 2020 -0600
  4. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  5. d3e6816 Revert "drivers/ddr/fsl: Dual-license DDR driver" by Tom Rini · Wed Feb 14 21:34:05 2018 -0500
  6. 6d49eda drivers/ddr/fsl: Dual-license DDR driver by York Sun · Wed Feb 07 11:47:22 2018 -0800
  7. fe84507 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS by York Sun · Wed Dec 28 08:43:45 2016 -0800
  8. 15875a5 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum by Shengzhou Liu · Mon Nov 21 11:36:48 2016 +0800
  9. e237880 Add more SPDX-License-Identifier tags by Tom Rini · Thu Jan 14 22:05:13 2016 -0500
  10. d957a67 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 by York Sun · Wed Nov 04 09:53:10 2015 -0800
  11. 999273f drivers/ddr/fsl: Adjust bstopre value by York Sun · Thu Jul 23 14:04:48 2015 -0700
  12. b10d1b7 driver/ddr/fsl: Add a hook to update SPD address by York Sun · Thu May 28 14:54:08 2015 +0530
  13. 55eb5fa drivers/ddr/fsl: Update DDR driver for DDR4 by York Sun · Thu Mar 19 09:30:26 2015 -0700
  14. 8ced050 driver/ddr/fsl: Add sync of refresh by York Sun · Tue Jan 06 13:18:55 2015 -0800
  15. 2c0b62d driver/ddr/fsl: Add support for multiple DDR clocks by York Sun · Tue Jan 06 13:18:50 2015 -0800
  16. 70acb34 arm/ls1021a: Add workaround for DDR erratum A008378 by York Sun · Mon Dec 08 15:30:55 2014 -0800
  17. 79a779b driver/ddr: Restruct driver to allow standalone memory space by York Sun · Fri Aug 01 15:51:00 2014 -0700
  18. 2896cb7 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · Thu Mar 27 17:54:47 2014 -0700
  19. 29647ab driver/ddr: Change Freescale ARM DDR driver to support both big and little endian by York Sun · Mon Feb 10 13:59:42 2014 -0800
  20. f062659 Driver/DDR: Moving Freescale DDR driver to a common driver by York Sun · Mon Sep 30 09:22:09 2013 -0700[Renamed (96%) from arch/powerpc/cpu/mpc8xxx/ddr/ddr.h]
  21. 4a71741 powerpc: Fix CamelCase warnings in DDR related code by Priyanka Jain · Wed Sep 25 10:41:19 2013 +0530
  22. 5e15555 powerpc/mpc8xxx: Add memory reset control by York Sun · Tue Jun 25 11:37:48 2013 -0700
  23. 4379438 powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands by James Yang · Mon Jan 07 14:01:03 2013 +0000
  24. bd495cf powerpc/8xxx: Add support for interactive DDR programming interface by York Sun · Fri Sep 16 13:21:35 2011 -0700
  25. e73cc04 powerpc/mpc8xxx: Enable calculation for fixed DDR chips by York Sun · Tue Jun 07 09:42:16 2011 +0800
  26. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  27. 27f83be powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 by York Sun · Thu Feb 10 10:13:10 2011 -0800
  28. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · Wed Dec 01 10:35:31 2010 -0500
  29. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  30. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ddr.h]
  31. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/ddr.h]
  32. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  33. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  34. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  35. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500