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git01.mediatek.com / filogic / uboot / 32dc389d4107ab3867adea85404bbcadb87214b1 / board / freescale / p1010rdb / ddr.c
  1. 5e15555 powerpc/mpc8xxx: Add memory reset control by York Sun · Tue Jun 25 11:37:48 2013 -0700
  2. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  3. a8b5739 ppc: Move lbc_clk and cpu to arch_global_data by Simon Glass · Thu Dec 13 20:48:48 2012 +0000
  4. c156f17 p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit) by Matthew McClintock · Mon Aug 13 08:10:38 2012 +0000
  5. 8cb6548 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER() by York Sun · Fri Jul 06 17:10:33 2012 -0500
  6. 66f0514 powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards by York Sun · Wed Feb 29 12:36:51 2012 +0000
  7. a2ec135 powerpc/85xx: Add basic support for P1010RDB by Poonam Aggrwal · Wed Feb 09 19:17:53 2011 +0000