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git01.mediatek.com / filogic / uboot / 324cb4d73d2883138305686b6f013e9e84de580d / arch / riscv / cpu / jh7110
  1. 2b62dd6 board: starfive: Rename spl_soc_init() to spl_dram_init() by Lukas Funke · Wed Apr 24 09:43:39 2024 +0200
  2. b6b9900 riscv: Remove common.h usage by Tom Rini · Thu Oct 12 19:03:59 2023 -0400
  3. 85621526 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT by Shengyu Qu · Fri Aug 25 00:25:20 2023 +0800
  4. 51a9aac common: return type board_get_usable_ram_top by Heinrich Schuchardt · Sat Aug 12 20:16:58 2023 +0200
  5. ac4bf43 riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:33 2023 +0800
  6. 62b89a1 riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation by Shengyu Qu · Wed Aug 09 21:11:32 2023 +0800
  7. 8fe34ac riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE by Minda Chen · Mon Aug 07 16:53:37 2023 +0800
  8. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  9. f69a512 ram: starfive: Read memory size information from EEPROM by Yanhong Wang · Thu Jun 15 17:36:51 2023 +0800
  10. 5203a63 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC by Yanhong Wang · Wed Mar 29 11:42:18 2023 +0800
  11. e28ec34 riscv: cpu: jh7110: Add support for jh7110 SoC by Yanhong Wang · Wed Mar 29 11:42:08 2023 +0800