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git01.mediatek.com / filogic / uboot / 31fdba2d80e8ec3038c6e6f6f9bcc76c79a5c385 / drivers / ddr
  1. 31fdba2 arm: mvebu: a38x: Weed out floating point use by Marek Vasut · Sat Apr 30 14:45:42 2016 +0200
  2. edfdb99 Fix spelling of "occurred". by Vagrant Cascadian · Sat Apr 30 19:18:00 2016 -0700
  3. 66acabc ddr: altera: Repair DQ window centering code by Marek Vasut · Tue Apr 05 23:17:35 2016 +0200
  4. a4b9fa1 ddr: altera: Staticize global variables by Marek Vasut · Tue Apr 05 11:18:38 2016 +0200
  5. 4df2d7b ddr: altera: Make DLEVEL behavior inclusive by Marek Vasut · Mon Apr 04 21:21:05 2016 +0200
  6. f4d3862 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() by Marek Vasut · Mon Apr 04 21:16:18 2016 +0200
  7. 2bf2ee5 ddr: altera: Remove unnecessary ODT mode config by Marek Vasut · Mon Apr 04 19:10:12 2016 +0200
  8. acee8fd ddr: altera: Remove unnecessary update of the SCC by Marek Vasut · Mon Apr 04 18:41:53 2016 +0200
  9. 12361a2 ddr: altera: Fix DRAM end value in protection rule by Marek Vasut · Mon Apr 04 17:52:21 2016 +0200
  10. 45ce296 ddr: altera: Fix scc_mgr_set() argument order by Marek Vasut · Mon Apr 04 17:28:16 2016 +0200
  11. 6946989 ddr: altera: Tweak DQS tracking enable handling by Marek Vasut · Tue Apr 05 23:41:56 2016 +0200
  12. 2654bc9 ddr: altera: Replace ad-hoc constant with macro by Marek Vasut · Mon Apr 04 16:07:11 2016 +0200
  13. 0137e60 Fix typo choosen in comments and printf logs by Alexander Merkle · Thu Mar 17 15:44:47 2016 +0100
  14. 5b2c16a arm: mvebu: Fix ddr3_init() cpu config by Dirk Eibach · Wed Oct 28 16:44:15 2015 +0100
  15. b03e1b1 driver/ddr/fsl: Add workaround for erratum A-009803 by Shengzhou Liu · Thu Mar 10 17:36:57 2016 +0800
  16. 5219944 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete by Shengzhou Liu · Thu Mar 10 17:36:56 2016 +0800
  17. 7557405 Use correct spelling of "U-Boot" by Bin Meng · Fri Feb 05 19:30:11 2016 -0800
  18. e80d11f drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32. by Purna Chandra Mandal · Thu Jan 28 15:30:15 2016 +0530
  19. 7ae7a0e drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers by Ed Swarthout · Thu Jan 14 12:28:04 2016 -0600
  20. bdda96c driver/ddr/fsl: Add workaround for A009663 by Shengzhou Liu · Wed Dec 16 16:45:41 2015 +0800
  21. fa2e2fb fsl/ddr: Add workaround for ERRATUM_A009942 by Shengzhou Liu · Wed Jan 06 11:26:51 2016 +0800
  22. e237880 Add more SPDX-License-Identifier tags by Tom Rini · Thu Jan 14 22:05:13 2016 -0500
  23. 42aa46d ddr: altera: Init the rule ID in debug code by Marek Vasut · Tue Dec 29 09:38:52 2015 +0100
  24. d911168 mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT by Phil Sutter · Fri Dec 25 14:41:23 2015 +0100
  25. 33aa8de axp: Fix debugging support in DDR3 write leveling by Phil Sutter · Fri Dec 25 14:41:19 2015 +0100
  26. ff7ad17 arm: mvebu: Make ECC support configurable on Armada XP by Stefan Roese · Thu Dec 10 15:02:38 2015 +0100
  27. 3c6b6fc arm: mvebu: ddr: Fix compilation warning by Stefan Roese · Thu Nov 19 13:50:10 2015 +0100
  28. fae8805 move erratum a008336 and a008514 to soc specific file by Yao Yuan · Sat Dec 05 14:59:14 2015 +0800
  29. 5a46e43 fsl/ddr: updated ddr errata-A008378 for arm and power SoCs by Shengzhou Liu · Fri Nov 20 15:52:04 2015 +0800
  30. 77594b3 driver/ddr/fsl: Update timing config for heavy load by York Sun · Wed Nov 04 10:03:21 2015 -0800
  31. 780ae3d driver/ddr/fsl: Update workaround for A008511 for vref range by York Sun · Wed Nov 04 10:03:20 2015 -0800
  32. d192126 driver/ddr/fsl: Update MR5 RTT park by York Sun · Wed Nov 04 10:03:19 2015 -0800
  33. d4d97ef driver/ddr/fsl: Update DDR4 MR6 for Vref range by York Sun · Wed Nov 04 10:03:18 2015 -0800
  34. 5cb12f6 driver/ddr/fsl: Update DDR4 RTT values by York Sun · Wed Nov 04 10:03:17 2015 -0800
  35. 68c19d7 drivers/ddr/fsl: Fix typo in BIST test for DDR4 by York Sun · Fri Nov 06 09:58:46 2015 -0800
  36. d957a67 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 by York Sun · Wed Nov 04 09:53:10 2015 -0800
  37. 77f7ded armv8: ls2085a: Add support of LS2085A SoC by Prabhakar Kushwaha · Mon Nov 09 16:42:20 2015 +0530
  38. 122bcfd armv8: LS2080A: Rename LS2085A to reflect LS2080A by Prabhakar Kushwaha · Mon Nov 09 16:42:07 2015 +0530
  39. dea4e33 arm: mvebu: Fix SAR1_CPU_CORE_MASK by Dirk Eibach · Wed Oct 28 16:44:14 2015 +0100
  40. 0277a6b arm: mvebu: a38x: Remove unsupported topologies by Kevin Smith · Fri Oct 23 17:53:19 2015 +0000
  41. 0cab3ec Various Makefiles: Add SPDX-License-Identifier tags by Tom Rini · Tue Nov 10 01:06:16 2015 +0000
  42. 6dc192d drivers/ddr/fsl_ddr: Make SR_IE configurable by Joakim Tjernlund · Wed Oct 14 16:32:00 2015 +0200
  43. 69bab55 bitops: introduce BIT() definition by Heiko Schocher · Mon Sep 07 13:43:52 2015 +0200
  44. eb447cb ddr: altera: Repair uninited variable by Marek Vasut · Mon Aug 10 23:01:43 2015 +0200
  45. af67cf3 ddr: altera: Replace float multiplication with integer one by Marek Vasut · Mon Aug 10 22:50:11 2015 +0200
  46. f3345e6 arm: mvebu: Add complete SDRAM ECC scrubbing by Stefan Roese · Thu Aug 06 14:43:13 2015 +0200
  47. e4a0f27 arm: mvebu: sdram: Enable ECC support on Armada XP by Stefan Roese · Tue Aug 11 17:08:01 2015 +0200
  48. c85b9b3 ddr: altera: sequencer: Clean checkpatch issues by Marek Vasut · Sun Aug 02 19:47:01 2015 +0200
  49. 8af9ca0 ddr: altera: sequencer: Clean data types by Marek Vasut · Sun Aug 02 19:42:26 2015 +0200
  50. 5867376 ddr: altera: sequencer: Pluck out misc macros from code by Marek Vasut · Sun Aug 02 19:26:55 2015 +0200
  51. 324d3f7 ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL by Marek Vasut · Sun Aug 02 19:24:12 2015 +0200
  52. 32d813e ddr: altera: sequencer: Zap VFIFO_SIZE by Marek Vasut · Sun Aug 02 19:21:56 2015 +0200
  53. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · Sun Aug 02 19:18:47 2015 +0200
  54. 7e8f8a7 ddr: altera: sequencer: Pluck out IO_* macros from code by Marek Vasut · Sun Aug 02 19:10:58 2015 +0200
  55. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · Sun Aug 02 19:00:23 2015 +0200
  56. 2dfc76b ddr: altera: sequencer: Pluck out RW_MGR_* macros from code by Marek Vasut · Sun Aug 02 18:44:06 2015 +0200
  57. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · Sun Aug 02 18:12:08 2015 +0200
  58. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · Sun Aug 02 17:15:19 2015 +0200
  59. 42ed1f2 ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS by Marek Vasut · Sun Aug 02 18:40:27 2015 +0200
  60. eb98b38 ddr: altera: sequencer: Zap unused params and macros by Marek Vasut · Sun Aug 02 18:27:21 2015 +0200
  61. 662a8a6 ddr: altera: sequencer: Move qts-generated files to board dir by Marek Vasut · Sun Aug 02 16:55:45 2015 +0200
  62. 6772cd9 ddr: altera: sdram: Make sdram_start and sdram_end into u32 by Marek Vasut · Sat Aug 01 23:12:11 2015 +0200
  63. 9114407 ddr: altera: sdram: Minor cleanup in sdram_get_rule() by Marek Vasut · Sat Aug 01 23:21:23 2015 +0200
  64. 7fce5bc ddr: altera: sdram: Minor cleanup in sdram_set_rule() by Marek Vasut · Sat Aug 01 22:40:48 2015 +0200
  65. b0d848c ddr: altera: sdram: Add missing kerneldoc by Marek Vasut · Sat Aug 01 22:28:30 2015 +0200
  66. 116d88f ddr: altera: sdram: Clean up sdram_write_verify() by Marek Vasut · Sat Aug 01 22:26:11 2015 +0200
  67. 1796a09 ddr: altera: sdram: Clean up sdram_calculate_size() part 2 by Marek Vasut · Sat Aug 01 21:47:16 2015 +0200
  68. 6d6fbba ddr: altera: sdram: Clean up sdram_calculate_size() part 1 by Marek Vasut · Sat Aug 01 21:44:00 2015 +0200
  69. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · Sat Aug 01 21:35:18 2015 +0200
  70. 1b1cc10 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8 by Marek Vasut · Sat Aug 01 22:25:29 2015 +0200
  71. 5a4e8ed ddr: altera: sdram: Clean up sdram_mmr_init_full() part 7 by Marek Vasut · Sat Aug 01 22:03:48 2015 +0200
  72. b81f11c ddr: altera: sdram: Clean up sdram_mmr_init_full() part 6 by Marek Vasut · Sat Aug 01 21:26:55 2015 +0200
  73. 1e271e4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5 by Marek Vasut · Sat Aug 01 21:24:31 2015 +0200
  74. 71c1a00 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4 by Marek Vasut · Sat Aug 01 21:21:21 2015 +0200
  75. 3a07911 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3 by Marek Vasut · Sat Aug 01 21:16:20 2015 +0200
  76. 7697ff7 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2 by Marek Vasut · Sat Aug 01 20:58:44 2015 +0200
  77. 4fccfa4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1 by Marek Vasut · Sat Aug 01 20:39:46 2015 +0200
  78. 4f3adbf ddr: altera: sdram: Introduce socfpga_sdram_config() structure by Marek Vasut · Sat Aug 01 20:30:10 2015 +0200
  79. 92e8e6f ddr: altera: sdram: Clean up set_sdr_mp_threshold() by Marek Vasut · Sat Aug 01 20:14:11 2015 +0200
  80. 44f09cc ddr: altera: sdram: Clean up set_sdr_mp_pacing() by Marek Vasut · Sat Aug 01 20:12:31 2015 +0200
  81. b933b19 ddr: altera: sdram: Clean up set_sdr_mp_weight() by Marek Vasut · Sat Aug 01 20:10:23 2015 +0200
  82. f904a86 ddr: altera: sdram: Clean up set_sdr_fifo_cfg() by Marek Vasut · Sat Aug 01 20:04:33 2015 +0200
  83. 9d64f19 ddr: altera: sdram: Clean up set_sdr_static_cfg() by Marek Vasut · Sat Aug 01 20:04:19 2015 +0200
  84. 820b0d9 ddr: altera: sdram: Clean up set_sdr_addr_rw() by Marek Vasut · Sat Aug 01 19:50:56 2015 +0200
  85. 6e9af9b ddr: altera: sdram: Clean up set_sdr_dram_timing*() by Marek Vasut · Sat Aug 01 19:45:24 2015 +0200
  86. 82a2764 ddr: altera: sdram: Clean up set_sdr_ctrlcfg() by Marek Vasut · Sat Aug 01 19:33:40 2015 +0200
  87. 724c50f ddr: altera: sdram: Clean up compute_errata_rows() part 2 by Marek Vasut · Sat Aug 01 19:20:19 2015 +0200
  88. 186880e ddr: altera: sdram: Clean up compute_errata_rows() part 1 by Marek Vasut · Sat Aug 01 18:54:34 2015 +0200
  89. 2fda506 ddr: altera: sdram: Switch to generic_hweight32() by Marek Vasut · Sat Aug 01 18:46:55 2015 +0200
  90. 98d279a ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 by Marek Vasut · Sun Jul 26 11:46:04 2015 +0200
  91. 7574c87 ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 by Marek Vasut · Sun Jul 26 11:44:54 2015 +0200
  92. 13ee438 ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 by Marek Vasut · Sun Jul 26 11:42:53 2015 +0200
  93. 4b203df ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 by Marek Vasut · Sun Jul 26 11:34:09 2015 +0200
  94. 50d7199 ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 by Marek Vasut · Sun Jul 26 11:11:28 2015 +0200
  95. c140275 ddr: altera: Minor clean up of rw_mgr_mem_handoff() by Marek Vasut · Sun Jul 26 10:59:19 2015 +0200
  96. a358127 ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() by Marek Vasut · Tue Jul 21 06:18:57 2015 +0200
  97. 2da0257 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() by Marek Vasut · Sat Jul 18 05:58:44 2015 +0200
  98. adbaa2d ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() by Marek Vasut · Tue Jul 21 06:00:36 2015 +0200
  99. c67d962 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 by Marek Vasut · Tue Jul 21 05:57:11 2015 +0200
  100. bc773a1 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 by Marek Vasut · Tue Jul 21 05:54:39 2015 +0200