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git01.mediatek.com / filogic / uboot / 2700b9c4e2f12bd79993141e585420251e5c14d5 / drivers / ddr
  1. 2700b9c ddr: altera: Clean up sdr_*_phase() part 7 by Marek Vasut · Sun Jul 19 05:40:06 2015 +0200
  2. 6da8ae4 ddr: altera: Clean up sdr_*_phase() part 6 by Marek Vasut · Sun Jul 19 05:35:40 2015 +0200
  3. f2b02d4 ddr: altera: Clean up sdr_*_phase() part 5 by Marek Vasut · Sun Jul 19 05:26:49 2015 +0200
  4. b148ebe ddr: altera: Clean up sdr_*_phase() part 4 by Marek Vasut · Sun Jul 19 05:01:12 2015 +0200
  5. 434f639 ddr: altera: Clean up sdr_*_phase() part 3 by Marek Vasut · Sun Jul 19 04:37:08 2015 +0200
  6. 6ff1c85 ddr: altera: Clean up sdr_*_phase() part 2 by Marek Vasut · Sun Jul 19 04:34:12 2015 +0200
  7. 139ad79 ddr: altera: Clean up sdr_*_phase() part 1 by Marek Vasut · Sun Jul 19 04:29:21 2015 +0200
  8. fea03c3 ddr: altera: Clean up sdr_find_window_centre() part 3 by Marek Vasut · Sun Jul 19 04:14:32 2015 +0200
  9. ea4c4bb ddr: altera: Clean up sdr_find_window_centre() part 2 by Marek Vasut · Sun Jul 19 04:04:33 2015 +0200
  10. d996e80 ddr: altera: Clean up sdr_find_window_centre() part 1 by Marek Vasut · Sun Jul 19 02:56:59 2015 +0200
  11. 3aa19dc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 by Marek Vasut · Sat Jul 18 04:28:42 2015 +0200
  12. 1beb243 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 by Marek Vasut · Sat Jul 18 04:24:49 2015 +0200
  13. faf820a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 by Marek Vasut · Sat Jul 18 04:20:26 2015 +0200
  14. bb9a5f7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 by Marek Vasut · Sat Jul 18 04:16:45 2015 +0200
  15. 55c4d69 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() by Marek Vasut · Sat Jul 18 03:55:07 2015 +0200
  16. fcef833 ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() by Marek Vasut · Sat Jul 18 03:36:09 2015 +0200
  17. 6a75278 ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup by Marek Vasut · Sat Jul 18 03:34:22 2015 +0200
  18. 349ea3e ddr: altera: Extract Centering DQ/DQS from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 03:10:31 2015 +0200
  19. feb5e65 ddr: altera: Extract DQS enable calibration from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:57:32 2015 +0200
  20. 6ca5b96 ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:46:56 2015 +0200
  21. 912d43e ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7 by Marek Vasut · Sat Jul 18 03:15:34 2015 +0200
  22. e42fcea ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6 by Marek Vasut · Fri Jul 17 04:24:18 2015 +0200
  23. 0d9f9d5 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5 by Marek Vasut · Fri Jul 17 03:54:34 2015 +0200
  24. f2a4bda ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4 by Marek Vasut · Fri Jul 17 03:50:17 2015 +0200
  25. d7f4915 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3 by Marek Vasut · Fri Jul 17 03:44:26 2015 +0200
  26. aff1a5f ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2 by Marek Vasut · Fri Jul 17 03:22:31 2015 +0200
  27. c27ea62 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1 by Marek Vasut · Fri Jul 17 03:16:45 2015 +0200
  28. 1185e22 ddr: altera: Minor clean up of rw_mgr_mem_initialize() by Marek Vasut · Sun Jul 26 10:57:06 2015 +0200
  29. d9fcf9a ddr: altera: Internal mem_calibrate() cleanup part 6 by Marek Vasut · Mon Jul 20 04:34:51 2015 +0200
  30. 0568f22 ddr: altera: Internal mem_calibrate() cleanup part 5 by Marek Vasut · Fri Jul 17 02:50:56 2015 +0200
  31. fc38d5c ddr: altera: Internal mem_calibrate() cleanup part 4 by Marek Vasut · Fri Jul 17 02:40:21 2015 +0200
  32. 6db5573 ddr: altera: Internal mem_calibrate() cleanup part 3 by Marek Vasut · Fri Jul 17 02:38:51 2015 +0200
  33. f04045f ddr: altera: Internal mem_calibrate() cleanup part 2 by Marek Vasut · Fri Jul 17 02:31:04 2015 +0200
  34. d6f2879 ddr: altera: Internal mem_calibrate() cleanup part 1 by Marek Vasut · Fri Jul 17 02:21:47 2015 +0200
  35. b984ee8 ddr: altera: Trivial mem_calibrate() indent cleanup by Marek Vasut · Fri Jul 17 02:07:12 2015 +0200
  36. 60daef8 ddr: altera: Minor clean up of mem_skip_calibrate() by Marek Vasut · Sun Jul 26 10:54:15 2015 +0200
  37. 575029d ddr: altera: Clean up set_rank_and_odt_mask() part 3 by Marek Vasut · Mon Jul 20 08:15:57 2015 +0200
  38. 9252308 ddr: altera: Clean up set_rank_and_odt_mask() part 2 by Marek Vasut · Mon Jul 20 08:09:05 2015 +0200
  39. 0b5e257 ddr: altera: Clean up set_rank_and_odt_mask() part 1 by Marek Vasut · Mon Jul 20 08:03:11 2015 +0200
  40. be333bc ddr: altera: Clean up mem_precharge_and_activate() by Marek Vasut · Mon Jul 20 07:33:33 2015 +0200
  41. 0f0840d ddr: altera: Clean up mem_config() by Marek Vasut · Fri Jul 17 01:57:41 2015 +0200
  42. fe5aa45 ddr: altera: Clean up phy_mgr_initialize() by Marek Vasut · Fri Jul 17 01:36:32 2015 +0200
  43. 092a1ef ddr: altera: Clean up run_mem_calibrate() by Marek Vasut · Fri Jul 17 01:20:21 2015 +0200
  44. acaaff7 ddr: altera: Rename initialize() to phy_mgr_initialize() by Marek Vasut · Fri Jul 17 01:12:07 2015 +0200
  45. 5da0f5b ddr: altera: Init my_param and my_gbl by Marek Vasut · Fri Jul 17 01:05:36 2015 +0200
  46. b0563cf ddr: altera: Rework initialize_tracking() by Marek Vasut · Fri Jul 17 00:45:11 2015 +0200
  47. e5f2cf7 ddr: altera: Fix ad-hoc iterative division implementation by Marek Vasut · Fri Jul 17 03:11:06 2015 +0200
  48. 42e7860 ddr: altera: Minor clean up of set_jump_as_return() by Marek Vasut · Sun Jul 26 11:07:19 2015 +0200
  49. c577ab5 ddr: altera: Factor out common code by Marek Vasut · Mon Jul 13 00:51:05 2015 +0200
  50. 8bf9227 ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize() by Marek Vasut · Mon Jul 13 00:44:30 2015 +0200
  51. 788870f ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks() by Marek Vasut · Sun Jul 19 02:18:21 2015 +0200
  52. 484fb3b ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2 by Marek Vasut · Fri Jul 17 05:33:28 2015 +0200
  53. 20bfb9d ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1 by Marek Vasut · Fri Jul 17 05:30:14 2015 +0200
  54. 62d3c69 ddr: altera: Clean up scc_mgr_zero_group() by Marek Vasut · Mon Jul 20 08:41:04 2015 +0200
  55. 08bcb98 ddr: altera: Clean up scc_mgr_zero_all() by Marek Vasut · Mon Jul 20 04:41:53 2015 +0200
  56. d4d3de2 ddr: altera: Extract scc_mgr_set_hhp_extras() by Marek Vasut · Sun Jul 19 01:34:43 2015 +0200
  57. 3b8e5b0 ddr: altera: Clean up scc_mgr_set_hhp_extras() by Marek Vasut · Sun Jul 19 01:32:55 2015 +0200
  58. 122e1f3 ddr: altera: Clean up scc_mgr_*_delay() args by Marek Vasut · Fri Jul 17 06:07:13 2015 +0200
  59. cd64950 ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay() by Marek Vasut · Fri Jul 17 05:42:49 2015 +0200
  60. e62f691 ddr: altera: Clean up scc_mgr_set_oct_out1_delay() by Marek Vasut · Sun Jul 12 23:39:06 2015 +0200
  61. 0341de4 ddr: altera: Clean up scc_set_bypass_mode() by Marek Vasut · Fri Jul 17 02:06:20 2015 +0200
  62. 5a4379e ddr: altera: Clean up scc_mgr_load_dqs_for_write_group() by Marek Vasut · Mon Jul 13 00:30:09 2015 +0200
  63. 1d3cde3 ddr: altera: Implement universal scc_mgr_set_all_ranks() by Marek Vasut · Sun Jul 12 23:25:21 2015 +0200
  64. 4972282 ddr: altera: Shuffle around scc_mgr_set_*all_ranks() by Marek Vasut · Sun Jul 12 23:14:33 2015 +0200
  65. 8957b49 ddr: altera: Clean up scc_mgr_initialize() by Marek Vasut · Mon Jul 20 07:16:42 2015 +0200
  66. 303a3dc ddr: altera: Implement universal scc manager config function by Marek Vasut · Sun Jul 12 22:28:33 2015 +0200
  67. 7481b69 ddr: altera: Reorder scc manager functions by Marek Vasut · Sun Jul 12 22:11:55 2015 +0200
  68. cab8079 ddr: altera: Clean up scc manager function args by Marek Vasut · Sun Jul 12 22:07:33 2015 +0200
  69. 6eeb747 ddr: altera: Clean up reg_file_set*() by Marek Vasut · Sun Jul 12 21:10:24 2015 +0200
  70. 0c9f3cb ddr: altera: Clean up initialize_hps_phy() by Marek Vasut · Sun Jul 19 06:14:04 2015 +0200
  71. a17ae0f ddr: altera: Clean up initialize_reg_file() by Marek Vasut · Sun Jul 19 06:13:37 2015 +0200
  72. ea9771b ddr: altera: Clean up hc_initialize_rom_data() by Marek Vasut · Sun Jul 19 06:12:42 2015 +0200
  73. b545096 ddr: altera: Massage addr into I/O accessors by Marek Vasut · Sun Jul 12 21:05:08 2015 +0200
  74. cd5d38e ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly by Marek Vasut · Sun Jul 12 20:49:39 2015 +0200
  75. 33acf0f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS by Marek Vasut · Sun Jul 12 20:05:54 2015 +0200
  76. a334010 ddr: altera: Pluck out remaining sdr_get_addr() calls by Marek Vasut · Sun Jul 12 19:03:33 2015 +0200
  77. c3b9b0f ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*) by Marek Vasut · Sun Jul 12 18:54:37 2015 +0200
  78. 0dcb9e8 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*) by Marek Vasut · Sun Jul 12 18:46:52 2015 +0200
  79. 81df0a2 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*) by Marek Vasut · Sun Jul 12 18:42:34 2015 +0200
  80. 341ceec ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*) by Marek Vasut · Sun Jul 12 18:31:05 2015 +0200
  81. 1fa9589 ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)" by Marek Vasut · Sun Jul 12 17:52:36 2015 +0200
  82. 6283b4c ddr: altera: Clean up ugly casts in sdram_calibration_full() by Marek Vasut · Mon Jul 13 01:05:27 2015 +0200
  83. f84348d ddr: altera: Minor indent fix in set_rank_and_odt_mask() by Marek Vasut · Sat Jul 18 02:23:29 2015 +0200
  84. 0eacf7e ddr: altera: Fix debug message format in sequencer by Marek Vasut · Fri Jun 26 18:56:54 2015 +0200
  85. 452d639 ddr: altera: Fix typo in mp_threshold1 programming by Marek Vasut · Thu Jul 09 01:47:56 2015 +0200
  86. e08c559 ddr: altera: Move struct sdram_prot_rule prototype by Marek Vasut · Sun Jul 26 10:37:54 2015 +0200
  87. 43bb47e arm: socfpga: Move sdram_config.h to board dir by Marek Vasut · Sun Jul 12 15:59:10 2015 +0200
  88. 135cc7f driver/ddr/altera: Add the sdram calibration portion by Dinh Nguyen · Tue Jun 02 22:52:49 2015 -0500
  89. 429642c driver/ddr/altera: Add DDR driver for Altera's SDRAM controller by Dinh Nguyen · Tue Jun 02 22:52:48 2015 -0500
  90. 999273f drivers/ddr/fsl: Adjust bstopre value by York Sun · Thu Jul 23 14:04:48 2015 -0700
  91. 61cee0a arm: mvebu: a38x: Use correct PEX register access macros by Stefan Roese · Mon Jun 08 17:01:26 2015 +0200
  92. 5ffceb8 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr by Stefan Roese · Thu Mar 26 15:36:56 2015 +0100
  93. eb753e9 arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory by Stefan Roese · Wed Mar 25 12:51:18 2015 +0100
  94. b10d1b7 driver/ddr/fsl: Add a hook to update SPD address by York Sun · Thu May 28 14:54:08 2015 +0530
  95. b1f81f0 arm: mvebu: db-mv784mp-gp: Fix ECC I2C address by Stefan Roese · Wed Apr 22 18:36:39 2015 +0200
  96. 1f8d706 driver/ddr/fsl: Add workaround for DDR erratum A008511 by York Sun · Thu Mar 19 09:30:29 2015 -0700
  97. b6a35f8 driver/ddr/fsl: Add built-in memory test for DDR4 driver by York Sun · Thu Mar 19 09:30:28 2015 -0700
  98. fc63b28 driver/ddr/fsl: Fix driver to support empty first slot by York Sun · Thu Mar 19 09:30:27 2015 -0700
  99. 55eb5fa drivers/ddr/fsl: Update DDR driver for DDR4 by York Sun · Thu Mar 19 09:30:26 2015 -0700
  100. 6aff153 MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register by Curt Brune · Fri Feb 13 10:57:11 2015 -0800