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git01.mediatek.com / filogic / uboot / 25657928770086b76b65acb14573d8d0e20eae9c / arch / arm / mach-tegra / tegra210 / clock.c
  1. b6ba3fb tegra: Correct logic for reading pll_misc in clock_start_pll() by Simon Glass · Mon Aug 10 07:14:36 2015 -0600
  2. a8480ef Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. by Tom Warren · Thu Jun 25 09:50:44 2015 -0700
  3. 27bce71 Tegra: clocks: Add 38.4MHz OSC support for T210 use by Tom Warren · Mon Jun 22 13:03:44 2015 -0700
  4. f80dd82 ARM: Tegra210: Add SoC code/include files for T210 by Tom Warren · Mon Feb 02 13:22:29 2015 -0700