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git01.mediatek.com / filogic / uboot / 1edc45f2eb85ed1da467a07fe9279c4e9c4db1f5 / arch / riscv / dts / jh7110-u-boot.dtsi
  1. 1345c9e riscv: dts: jh7110: Add clock source from PLL by Xingyu Wu · Fri Jul 07 18:50:09 2023 +0800
  2. 94817bf riscv: dts: jh7110: Add initial u-boot device tree by Yanhong Wang · Wed Mar 29 11:42:22 2023 +0800