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git01.mediatek.com / filogic / uboot / 173a108b1641cced14141a117f400b7ca9239007 / cpu / mpc8xxx / ddr
  1. 45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  2. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · 16 years ago
  3. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  4. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  5. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  6. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  7. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  8. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  9. b834f92 Check DDR interleaving mode by Haiying Wang · 16 years ago
  10. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  11. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  12. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  13. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  14. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  15. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  16. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  17. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago