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git01.mediatek.com
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filogic
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uboot
/
14e6696bf10aa702fcdea059e266bc95cbe61c99
/
drivers
/
clk
/
renesas
/
r8a7796-cpg-mssr.c
f6b3202
clk: renesas: Add and enable CPG reset driver
by Marek Vasut
· Thu Jan 26 21:02:03 2023 +0100
f144d50
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
by Hai Pham
· Thu Jan 26 21:02:02 2023 +0100
fd44059
clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7
by Marek Vasut
· Thu Jan 26 21:01:51 2023 +0100
814217e
clk: renesas: Make reset controller modemr register offset configurable
by Marek Vasut
· Sun Apr 25 21:53:05 2021 +0200
0e8dcb7
clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12
by Marek Vasut
· Sun Apr 25 21:10:40 2021 +0200
22f9fc7
clk: renesas: Only ever access documented bits in clock driver teardown
by Marek Vasut
· Sat Apr 25 14:57:45 2020 +0200
8a2b47f
dm: treewide: Rename auto_alloc_size members to be shorter
by Simon Glass
· Thu Dec 03 16:55:17 2020 -0700
4dcacfc
common: Drop linux/bitops.h from common header
by Simon Glass
· Sun May 10 11:40:13 2020 -0600
7841483
clk: renesas: Synchronize Gen3 tables with Linux 5.0
by Marek Vasut
· Mon Mar 04 21:38:10 2019 +0100
98c2058
clk: renesas: Add R8A77965 clock tables
by Marek Vasut
· Mon Mar 04 13:36:13 2019 +0100
10e4779
SPDX: Convert all of our single license tags to Linux Kernel style
by Tom Rini
· Sun May 06 17:58:06 2018 -0400
284e94c
clk: renesas: Add R8A77965 M3N entries
by Marek Vasut
· Mon Feb 26 10:35:15 2018 +0100
2eb56a1
clk: renesas: Split SMSTPCR and RMSTPCR tables
by Marek Vasut
· Mon Jan 15 00:58:35 2018 +0100
7ef12c2
clk: renesas: Pull Gen3 specific bits into separate header
by Marek Vasut
· Mon Jan 08 17:09:45 2018 +0100
28f9004
clk: renesas: Make PLL configurations per-SoC
by Marek Vasut
· Tue Jan 16 19:23:17 2018 +0100
b923419
clk: renesas: Make clk_ids per-driver
by Marek Vasut
· Mon Jan 08 16:05:28 2018 +0100
4eb4e6e
clk: renesas: Split RCar Gen3 driver
by Marek Vasut
· Mon Jan 08 14:01:40 2018 +0100